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Renesas ARM DT updates for v5.8 (take two)

Browse Source 
- Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
     Qseven SOM (G21M) and board (G21D),
   - Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
     Silicon Linux EK874 RZ/G2E evaluation kit.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXr5g8QAKCRCKwlD9ZEnx
 cDusAQD4SCmyY0MZZNWQhkhu2ics2wYpKItw4Y7E4fl9XUlXkQEAyyN11vVNoteX
 7KvNX7/9eXpberlcx4H6szPQsOzWzwM=
 =2KDk
 -----END PGP SIGNATURE-----

Merge tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.8 (take two)

  - Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
    Qseven SOM (G21M) and board (G21D),
  - Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
    Silicon Linux EK874 RZ/G2E evaluation kit.

* tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
  ARM: dts: r8a7742: Add GPIO nodes
  ARM: dts: r8a7742: Add [H]SCIF{A|B} support
  ARM: dts: r8a7742: Add IRQC support
  ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
  ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
  ARM: dts: r8a7742: Initial SoC device tree
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros

Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-21 16:02:11 +02:00
commit de12d92147
9 changed files with 978 additions and 1 deletions
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1
arch/arm/boot/dts/Makefile
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@ -923,6 +923,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r7s9210-rza2mevb.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7742-iwg21d-q7.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \

37
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts Normal file
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@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the iWave-RZ/G1H Qseven board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a7742-iwg21m.dtsi"
/ {
model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
aliases {
serial2 = &scifa2;
};
chosen {
bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait";
stdout-path = "serial2:115200n8";
};
};
&pfc {
scifa2_pins: scifa2 {
groups = "scifa2_data_c";
function = "scifa2";
};
};
&scifa2 {
pinctrl-0 = <&scifa2_pins>;
pinctrl-names = "default";
status = "okay";
};

53
arch/arm/boot/dts/r8a7742-iwg21m.dtsi Normal file
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@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the iWave RZ/G1H Qseven SOM
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a7742.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "iwave,g21m", "renesas,r8a7742";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
memory@200000000 {
device_type = "memory";
reg = <2 0x00000000 0 0x40000000>;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&pfc {
mmc1_pins: mmc1 {
groups = "mmc1_data4", "mmc1_ctrl";
function = "mmc1";
};
};
&mmcif1 {
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
bus-width = <4>;
non-removable;
status = "okay";
};

648
arch/arm/boot/dts/r8a7742.dtsi Normal file
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@ -0,0 +1,648 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a7742 SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7742-sysc.h>
/ {
compatible = "renesas,r8a7742";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
/* kHz - uV - OPPs unknown yet */
operating-points = <1400000 1000000>,
<1225000 1000000>,
<1050000 1000000>,
< 875000 1000000>,
< 700000 1000000>,
< 350000 1000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
/* kHz - uV - OPPs unknown yet */
operating-points = <1400000 1000000>,
<1225000 1000000>,
<1050000 1000000>,
< 875000 1000000>,
< 700000 1000000>,
< 350000 1000000>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
/* kHz - uV - OPPs unknown yet */
operating-points = <1400000 1000000>,
<1225000 1000000>,
<1050000 1000000>,
< 875000 1000000>,
< 700000 1000000>,
< 350000 1000000>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
/* kHz - uV - OPPs unknown yet */
operating-points = <1400000 1000000>,
<1225000 1000000>,
<1050000 1000000>,
< 875000 1000000>,
< 700000 1000000>,
< 350000 1000000>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
next-level-cache = <&L2_CA7>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
next-level-cache = <&L2_CA7>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
next-level-cache = <&L2_CA7>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
next-level-cache = <&L2_CA7>;
};
L2_CA15: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A7742_PD_CA15_SCU>;
cache-unified;
cache-level = <2>;
};
L2_CA7: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc R8A7742_PD_CA7_SCU>;
cache-unified;
cache-level = <2>;
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
pmu-1 {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 30>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 30>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7742";
reg = <0 0xe6060000 0 0x250>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7742-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&usb_extal_clk>;
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7742-rst";
reg = <0 0xe6160000 0 0x0100>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7742-sysc";
reg = <0 0xe6180000 0 0x0200>;
#power-domain-cells = <1>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7742", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x100>;
};
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe6300000 0x40000>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7742",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
dmac1: dma-controller@e6720000 {
compatible = "renesas,dmac-r8a7742",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7742",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c40000 0 0x40>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>;
clock-names = "fck";
dmas = <&dmac0 0x21>, <&dmac0 0x22>,
<&dmac1 0x21>, <&dmac1 0x22>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
scifa1: serial@e6c50000 {
compatible = "renesas,scifa-r8a7742",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c50000 0 0x40>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>;
clock-names = "fck";
dmas = <&dmac0 0x25>, <&dmac0 0x26>,
<&dmac1 0x25>, <&dmac1 0x26>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
scifa2: serial@e6c60000 {
compatible = "renesas,scifa-r8a7742",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c60000 0 0x40>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 202>;
clock-names = "fck";
dmas = <&dmac0 0x27>, <&dmac0 0x28>,
<&dmac1 0x27>, <&dmac1 0x28>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7742",
"renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6c20000 0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>;
clock-names = "fck";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
<&dmac1 0x3d>, <&dmac1 0x3e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a7742",
"renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6c30000 0 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>;
clock-names = "fck";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
<&dmac1 0x19>, <&dmac1 0x1a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a7742",
"renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6ce0000 0 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 216>;
clock-names = "fck";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
<&dmac1 0x1d>, <&dmac1 0x1e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 216>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7742",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 721>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a7742",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 720>,
<&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 720>;
status = "disabled";
};
scif2: serial@e6e56000 {
compatible = "renesas,scif-r8a7742",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e56000 0 0x40>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
hscif0: serial@e62c0000 {
compatible = "renesas,hscif-r8a7742",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c0000 0 0x60>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 717>,
<&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
<&dmac1 0x39>, <&dmac1 0x3a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 717>;
status = "disabled";
};
hscif1: serial@e62c8000 {
compatible = "renesas,hscif-r8a7742",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c8000 0 0x60>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>,
<&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
<&dmac1 0x4d>, <&dmac1 0x4e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
};
mmcif1: mmc@ee220000 {
compatible = "renesas,mmcif-r8a7742",
"renesas,sh-mmcif";
reg = <0 0xee220000 0 0x80>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 305>;
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
<&dmac1 0xe1>, <&dmac1 0xe2>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 305>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};

3
arch/arm64/boot/dts/renesas/Makefile
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@ -5,7 +5,8 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
r8a774c0-ek874-idk-2121wr.dtb
r8a774c0-ek874-idk-2121wr.dtb \
r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb

94
arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi Normal file
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@ -0,0 +1,94 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the AISTARVISION MIPI Adapter V2.1
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/ {
ov5645_vdddo_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ov5645_vdda_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ov5645_vddd_1v5: 1p5v {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
imx219_vana_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vana";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
imx219_vdig_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdig";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
imx219_vddl_1v2: 1p2v {
compatible = "regulator-fixed";
regulator-name = "camera_vddl";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
osc25250_clk: osc25250_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&MIPI_PARENT_I2C {
ov5645: ov5645@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
clock-names = "xclk";
clocks = <&osc25250_clk>;
clock-frequency = <24000000>;
vdddo-supply = <&ov5645_vdddo_1v8>;
vdda-supply = <&ov5645_vdda_2v8>;
vddd-supply = <&ov5645_vddd_1v5>;
port {
ov5645_ep: endpoint {
};
};
};
imx219: imx219@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&osc25250_clk>;
VANA-supply = <&imx219_vana_2v8>;
VDIG-supply = <&imx219_vdig_1v8>;
VDDL-supply = <&imx219_vddl_1v2>;
port {
imx219_ep: endpoint {
};
};
};
};

72
arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774c0-ek874.dts"
#define MIPI_PARENT_I2C i2c3
#include "aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-adapter board";
compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
};
&i2c3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&csi40 {
status = "okay";
ports {
port {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&ov5645_ep>;
};
};
};
};
&ov5645 {
enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
port {
ov5645_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
&imx219 {
port {
imx219_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
/* uncomment remote-endpoint property to tie imx219 to
* CSI2 also make sure remote-endpoint for ov5645 camera
* is commented and remote endpoint phandle in csi40_in
* is imx219_ep
*/
/* remote-endpoint = <&csi40_in>; */
};
};
};

42
include/dt-bindings/clock/r8a7742-cpg-mssr.h Normal file
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@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7742 CPG Core Clocks */
#define R8A7742_CLK_Z 0
#define R8A7742_CLK_Z2 1
#define R8A7742_CLK_ZG 2
#define R8A7742_CLK_ZTR 3
#define R8A7742_CLK_ZTRD2 4
#define R8A7742_CLK_ZT 5
#define R8A7742_CLK_ZX 6
#define R8A7742_CLK_ZS 7
#define R8A7742_CLK_HP 8
#define R8A7742_CLK_B 9
#define R8A7742_CLK_LB 10
#define R8A7742_CLK_P 11
#define R8A7742_CLK_CL 12
#define R8A7742_CLK_M2 13
#define R8A7742_CLK_ZB3 14
#define R8A7742_CLK_ZB3D2 15
#define R8A7742_CLK_DDR 16
#define R8A7742_CLK_SDH 17
#define R8A7742_CLK_SD0 18
#define R8A7742_CLK_SD1 19
#define R8A7742_CLK_SD2 20
#define R8A7742_CLK_SD3 21
#define R8A7742_CLK_MMC0 22
#define R8A7742_CLK_MMC1 23
#define R8A7742_CLK_MP 24
#define R8A7742_CLK_QSPI 25
#define R8A7742_CLK_CP 26
#define R8A7742_CLK_RCAN 27
#define R8A7742_CLK_R 28
#define R8A7742_CLK_OSC 29
#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */

29
include/dt-bindings/power/r8a7742-sysc.h Normal file
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@ -0,0 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7742_PD_CA15_CPU0 0
#define R8A7742_PD_CA15_CPU1 1
#define R8A7742_PD_CA15_CPU2 2
#define R8A7742_PD_CA15_CPU3 3
#define R8A7742_PD_CA7_CPU0 5
#define R8A7742_PD_CA7_CPU1 6
#define R8A7742_PD_CA7_CPU2 7
#define R8A7742_PD_CA7_CPU3 8
#define R8A7742_PD_CA15_SCU 12
#define R8A7742_PD_RGX 20
#define R8A7742_PD_CA7_SCU 21
/* Always-on power area */
#define R8A7742_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */