forked from luck/tmp_suning_uos_patched
drm/exynos: add support for exynos5420 mixer
Add support for exynos5420 mixer IP in the drm mixer driver. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Seung-Woo Kim <sw0312.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -5,6 +5,7 @@ Required properties:
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1) "samsung,exynos5-mixer" <DEPRECATED>
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2) "samsung,exynos4210-mixer"
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3) "samsung,exynos5250-mixer"
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4) "samsung,exynos5420-mixer"
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- reg: physical base address of the mixer and length of memory mapped
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region.
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@ -78,6 +78,7 @@ struct mixer_resources {
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enum mixer_version_id {
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MXR_VER_0_0_0_16,
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MXR_VER_16_0_33_0,
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MXR_VER_128_0_0_184,
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};
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struct mixer_context {
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@ -283,17 +284,19 @@ static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
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val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
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MXR_CFG_SCAN_PROGRASSIVE);
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/* choosing between porper HD and SD mode */
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if (height <= 480)
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val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
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else if (height <= 576)
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val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
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else if (height <= 720)
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val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
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else if (height <= 1080)
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val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
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else
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val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
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if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
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/* choosing between proper HD and SD mode */
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if (height <= 480)
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val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
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else if (height <= 576)
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val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
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else if (height <= 720)
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val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
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else if (height <= 1080)
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val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
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else
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val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
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}
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mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
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}
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@ -557,6 +560,14 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
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/* setup geometry */
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mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
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/* setup display size */
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if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
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win == MIXER_DEFAULT_WIN) {
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val = MXR_MXR_RES_HEIGHT(win_data->fb_height);
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val |= MXR_MXR_RES_WIDTH(win_data->fb_width);
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mixer_reg_write(res, MXR_RESOLUTION, val);
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}
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val = MXR_GRP_WH_WIDTH(win_data->crtc_width);
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val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height);
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val |= MXR_GRP_WH_H_SCALE(x_ratio);
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@ -581,7 +592,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
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mixer_cfg_layer(ctx, win, true);
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/* layer update mandatory for mixer 16.0.33.0 */
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if (ctx->mxr_ver == MXR_VER_16_0_33_0)
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if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
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ctx->mxr_ver == MXR_VER_128_0_0_184)
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mixer_layer_update(ctx);
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mixer_run(ctx);
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@ -816,6 +828,7 @@ static void mixer_win_disable(void *ctx, int win)
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static int mixer_check_mode(void *ctx, struct drm_display_mode *mode)
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{
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struct mixer_context *mixer_ctx = ctx;
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u32 w, h;
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w = mode->hdisplay;
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@ -825,6 +838,10 @@ static int mixer_check_mode(void *ctx, struct drm_display_mode *mode)
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mode->hdisplay, mode->vdisplay, mode->vrefresh,
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(mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
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if (mixer_ctx->mxr_ver == MXR_VER_0_0_0_16 ||
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mixer_ctx->mxr_ver == MXR_VER_128_0_0_184)
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return 0;
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if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
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(w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
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(w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
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@ -1115,6 +1132,11 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx,
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return 0;
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}
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static struct mixer_drv_data exynos5420_mxr_drv_data = {
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.version = MXR_VER_128_0_0_184,
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.is_vp_enabled = 0,
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};
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static struct mixer_drv_data exynos5250_mxr_drv_data = {
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.version = MXR_VER_16_0_33_0,
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.is_vp_enabled = 0,
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@ -1144,6 +1166,9 @@ static struct of_device_id mixer_match_types[] = {
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}, {
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.compatible = "samsung,exynos5250-mixer",
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.data = &exynos5250_mxr_drv_data,
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}, {
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.compatible = "samsung,exynos5420-mixer",
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.data = &exynos5420_mxr_drv_data,
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}, {
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/* end node */
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}
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@ -44,6 +44,9 @@
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#define MXR_CM_COEFF_Y 0x0080
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#define MXR_CM_COEFF_CB 0x0084
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#define MXR_CM_COEFF_CR 0x0088
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#define MXR_MO 0x0304
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#define MXR_RESOLUTION 0x0310
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#define MXR_GRAPHIC0_BASE_S 0x2024
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#define MXR_GRAPHIC1_BASE_S 0x2044
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@ -119,6 +122,10 @@
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#define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16)
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#define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)
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/* bits for MXR_RESOLUTION */
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#define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16)
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#define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0)
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/* bits for MXR_GRAPHICn_SXY */
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#define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16)
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#define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0)
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