forked from luck/tmp_suning_uos_patched
First round of amlogic clock updates for v5.7
* Update audio clock gate hierarchy for meson8 and gxbb * Update g12a spicc clock sources -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl5gx9sACgkQ5vwPHDfy 2oXbsg//UjqnFvtyP2DsbCBjjhVBs6YcGgUnC9+2jaCmbyR0SbsZovF1a31PILt1 yHL0JEvlSkO+5qKnp/s8Ff13wgDAz5QhEp5MXvRBBqU7zKksBUB2NhEzuMOFzVqA 79uaLcStGza8tjjOR+Qg3WDuZZsEVWGI1pTX0Vj6TnonUhRlcoN0mFVZa3/zya2+ GER0WaDJUCrbjT3Sm3M0ZzpfV/XKtu+9BDLmVLoG0weyLB4lrQdSlVHLz0mf2XS0 gVtEMnj57n5x3nkrdB9OYX0LSydPqMiYYho5dMh6WQ1QFjeHBheS0mCJFxdKrSWM 89obpP5CZYFa5Lvoboh516fwo/hA/KpdqAVmauIuxHqIQ5ZLAwfFJ7e8c8YMpDRw JEJy5fXShFJy5utbk4UZs8X30p+X2RgKhXFc2KdyuZ6UEo2wRxfvOFvumDt41RVX +onHnqF0UCBBuPepc9TNtfw3qH6qG9KsnRfNfIydMdIO2A/MSKu2TbCyYsiVkm3w W5enEOUIY+cSZ35fTDzVXotwXLW+7uYosvcEa/KlEHgQ9gzkrTGagKtj8eY4xFgZ i54rlY49SoivIRPrNR68bPQSDNHSgyLOH52kp7m2sa7633UAvbmnxwHKx8S3ZWlM 0EmS6J0KAIItpan4t2ujsWfxMjwcugFRApZ4orx1fTUDzEB3vb8= =14dC -----END PGP SIGNATURE----- Merge tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Update audio clock gate hierarchy for meson8 and gxbb - Update g12a spicc clock sources * tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate
This commit is contained in:
Stephen Boyd
commit
dfbfee8702
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@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = {
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},
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};
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/* SPICC SCLK source clock */
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static const struct clk_parent_data spicc_sclk_parent_data[] = {
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{ .fw_name = "xtal", },
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{ .hw = &g12a_clk81.hw },
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{ .hw = &g12a_fclk_div4.hw },
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{ .hw = &g12a_fclk_div3.hw },
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{ .hw = &g12a_fclk_div5.hw },
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{ .hw = &g12a_fclk_div7.hw },
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};
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static struct clk_regmap g12a_spicc0_sclk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SPICC_CLK_CNTL,
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.mask = 7,
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.shift = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "spicc0_sclk_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_data = spicc_sclk_parent_data,
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.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
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},
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};
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static struct clk_regmap g12a_spicc0_sclk_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SPICC_CLK_CNTL,
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.shift = 0,
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.width = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "spicc0_sclk_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_spicc0_sclk_sel.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_spicc0_sclk = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SPICC_CLK_CNTL,
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.bit_idx = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "spicc0_sclk",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_spicc0_sclk_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_spicc1_sclk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SPICC_CLK_CNTL,
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.mask = 7,
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.shift = 23,
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},
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.hw.init = &(struct clk_init_data){
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.name = "spicc1_sclk_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_data = spicc_sclk_parent_data,
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.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
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},
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};
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static struct clk_regmap g12a_spicc1_sclk_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SPICC_CLK_CNTL,
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.shift = 16,
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.width = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "spicc1_sclk_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_spicc1_sclk_sel.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_spicc1_sclk = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SPICC_CLK_CNTL,
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.bit_idx = 22,
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},
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.hw.init = &(struct clk_init_data){
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.name = "spicc1_sclk",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_spicc1_sclk_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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#define MESON_GATE(_name, _reg, _bit) \
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MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
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@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
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[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
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[CLKID_TS_DIV] = &g12a_ts_div.hw,
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[CLKID_TS] = &g12a_ts.hw,
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[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
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[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
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[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
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[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
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[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
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[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
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[CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
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[CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
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[CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
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[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
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[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
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[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
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[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
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[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
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[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
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[CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
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[CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
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[CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
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[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
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[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
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[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
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[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
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[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
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[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
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&sm1_cpu1_clk,
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&sm1_cpu2_clk,
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&sm1_cpu3_clk,
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&g12a_spicc0_sclk_sel,
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&g12a_spicc0_sclk_div,
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&g12a_spicc0_sclk,
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&g12a_spicc1_sclk_sel,
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&g12a_spicc1_sclk_div,
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&g12a_spicc1_sclk,
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};
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static const struct reg_sequence g12a_init_regs[] = {
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@ -255,8 +255,12 @@
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#define CLKID_DSU_CLK_DYN1 249
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#define CLKID_DSU_CLK_DYN 250
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#define CLKID_DSU_CLK_FINAL 251
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#define CLKID_SPICC0_SCLK_SEL 256
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#define CLKID_SPICC0_SCLK_DIV 257
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#define CLKID_SPICC1_SCLK_SEL 259
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#define CLKID_SPICC1_SCLK_DIV 260
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#define NR_CLKS 256
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#define NR_CLKS 262
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/g12a-clkc.h>
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@ -2613,19 +2613,12 @@ static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
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static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
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static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
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static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
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static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
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static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
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static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
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static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
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static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
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static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
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static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
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static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
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static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
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static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
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static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
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static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
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static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
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static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
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static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
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static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
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@ -2680,6 +2673,16 @@ static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
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static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
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static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
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/* AIU gates */
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static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
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static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
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static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
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static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
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static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
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static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
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static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
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static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
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/* Array of all clocks provided by this provider */
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static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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@ -3100,6 +3103,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
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[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
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[CLKID_HDMI] = &gxbb_hdmi.hw,
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[CLKID_ACODEC] = &gxl_acodec.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -3491,6 +3495,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
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&gxl_hdmi_pll_od,
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&gxl_hdmi_pll_od2,
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&gxl_hdmi_pll_dco,
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&gxl_acodec,
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};
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static const struct meson_eeclkc_data gxbb_clkc_data = {
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@ -188,7 +188,7 @@
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#define CLKID_HDMI_SEL 203
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#define CLKID_HDMI_DIV 204
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#define NR_CLKS 206
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#define NR_CLKS 207
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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@ -2605,14 +2605,6 @@ static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
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static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
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static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
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static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
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static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
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static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
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static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
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static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
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static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
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static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
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static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
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static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
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static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
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static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
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static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
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@ -2659,6 +2651,19 @@ static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
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static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
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static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
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/* AIU gates */
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#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
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MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
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static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
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static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
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static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
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static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
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static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
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static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
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static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
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static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
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/* Always On (AO) domain gates */
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static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
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@ -143,5 +143,7 @@
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#define CLKID_CPU1_CLK 253
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#define CLKID_CPU2_CLK 254
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#define CLKID_CPU3_CLK 255
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#define CLKID_SPICC0_SCLK 258
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#define CLKID_SPICC1_SCLK 261
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#endif /* __G12A_CLKC_H */
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|||
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|
@ -146,5 +146,6 @@
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#define CLKID_CTS_VDAC 201
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#define CLKID_HDMI_TX 202
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#define CLKID_HDMI 205
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#define CLKID_ACODEC 206
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||||
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||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user