forked from luck/tmp_suning_uos_patched
[MMC] sdhci: fix sdhci reset timeout
The reset register is automatically cleared when the reset has completed. Hence, we should busy wait and not have a fixed delay. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -94,12 +94,27 @@ static void sdhci_dumpregs(struct sdhci_host *host)
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static void sdhci_reset(struct sdhci_host *host, u8 mask)
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static void sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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{
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unsigned long timeout;
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writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
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writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
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if (mask & SDHCI_RESET_ALL) {
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if (mask & SDHCI_RESET_ALL)
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host->clock = 0;
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host->clock = 0;
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mdelay(50);
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/* Wait max 100 ms */
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timeout = 100;
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/* hw clears the bit when it's done */
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while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
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if (timeout == 0) {
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printk(KERN_ERR "%s: Reset 0x%x never completed. "
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"Please report this to " BUGMAIL ".\n",
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mmc_hostname(host->mmc), (int)mask);
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sdhci_dumpregs(host);
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return;
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}
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timeout--;
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mdelay(1);
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}
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}
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}
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}
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@ -619,9 +634,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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*/
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*/
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if (ios->power_mode == MMC_POWER_OFF) {
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if (ios->power_mode == MMC_POWER_OFF) {
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writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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spin_unlock_irqrestore(&host->lock, flags);
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sdhci_init(host);
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sdhci_init(host);
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spin_lock_irqsave(&host->lock, flags);
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}
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}
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sdhci_set_clock(host, ios->clock);
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sdhci_set_clock(host, ios->clock);
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