forked from luck/tmp_suning_uos_patched
[POWERPC] Add Marvell mv64x60 PCI bridge support
This patch adds PCI bridge support for the Marvell mv64x60 chip. We also provide the ability to read/write the mv64x60 hotswap register via sysfs if the hs_reg_valid property is set in the device tree. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
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01f0e78e15
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@ -48,6 +48,7 @@ config MPC10X_BRIDGE
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config MV64X60
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bool
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select PPC_INDIRECT_PCI
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config MPC10X_OPENPIC
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bool
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@ -16,7 +16,8 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
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obj-$(CONFIG_MV64X60) += mv64x60_pic.o mv64x60_dev.o
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mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
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obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o
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# contains only the suspend handler for time
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obj-$(CONFIG_PM) += timer.o
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@ -6,4 +6,6 @@
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extern void __init mv64x60_init_irq(void);
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extern unsigned int mv64x60_get_irq(void);
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extern void __init mv64x60_pci_init(void);
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#endif /* __MV64X60_H__ */
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172
arch/powerpc/sysdev/mv64x60_pci.c
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172
arch/powerpc/sysdev/mv64x60_pci.c
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@ -0,0 +1,172 @@
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/*
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* PCI bus setup for Marvell mv64360/mv64460 host bridges (Discovery)
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*
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* Author: Dale Farnsworth <dale@farnsworth.org>
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*
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* 2007 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#define PCI_HEADER_TYPE_INVALID 0x7f /* Invalid PCI header type */
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#ifdef CONFIG_SYSFS
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/* 32-bit hex or dec stringified number + '\n' */
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#define MV64X60_VAL_LEN_MAX 11
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#define MV64X60_PCICFG_CPCI_HOTSWAP 0x68
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static ssize_t mv64x60_hs_reg_read(struct kobject *kobj, char *buf, loff_t off,
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size_t count)
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{
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struct pci_dev *phb;
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u32 v;
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if (off > 0)
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return 0;
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if (count < MV64X60_VAL_LEN_MAX)
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return -EINVAL;
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phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
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if (!phb)
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return -ENODEV;
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pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v);
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pci_dev_put(phb);
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return sprintf(buf, "0x%08x\n", v);
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}
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static ssize_t mv64x60_hs_reg_write(struct kobject *kobj, char *buf, loff_t off,
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size_t count)
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{
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struct pci_dev *phb;
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u32 v;
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if (off > 0)
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return 0;
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if (count <= 0)
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return -EINVAL;
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if (sscanf(buf, "%i", &v) != 1)
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return -EINVAL;
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phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
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if (!phb)
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return -ENODEV;
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pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v);
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pci_dev_put(phb);
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return count;
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}
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static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
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.attr = {
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.name = "hs_reg",
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.mode = S_IRUGO | S_IWUSR,
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.owner = THIS_MODULE,
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},
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.size = MV64X60_VAL_LEN_MAX,
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.read = mv64x60_hs_reg_read,
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.write = mv64x60_hs_reg_write,
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};
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static int __init mv64x60_sysfs_init(void)
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{
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struct device_node *np;
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struct platform_device *pdev;
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const unsigned int *prop;
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np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60");
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if (!np)
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return 0;
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prop = of_get_property(np, "hs_reg_valid", NULL);
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of_node_put(np);
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pdev = platform_device_register_simple("marvell,mv64x60", 0, NULL, 0);
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if (IS_ERR(pdev))
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return PTR_ERR(pdev);
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return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr);
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}
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subsys_initcall(mv64x60_sysfs_init);
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#endif /* CONFIG_SYSFS */
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static void __init mv64x60_pci_fixup_early(struct pci_dev *dev)
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{
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/*
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* Set the host bridge hdr_type to an invalid value so that
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* pci_setup_device() will ignore the host bridge.
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*/
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dev->hdr_type = PCI_HEADER_TYPE_INVALID;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360,
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mv64x60_pci_fixup_early);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64460,
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mv64x60_pci_fixup_early);
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static int __init mv64x60_add_bridge(struct device_node *dev)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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int primary;
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memset(&rsrc, 0, sizeof(rsrc));
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/* Fetch host bridge registers address */
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if (of_address_to_resource(dev, 0, &rsrc)) {
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printk(KERN_ERR "No PCI reg property in device tree\n");
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return -ENODEV;
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}
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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hose = pcibios_alloc_controller();
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if (!hose)
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return -ENOMEM;
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hose->arch_data = dev;
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hose->set_cfg_type = 1;
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 4);
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hose->bus_offset = hose->first_busno;
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printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
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"Firmware bus number: %d->%d\n",
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(unsigned long long)rsrc.start, hose->first_busno,
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hose->last_busno);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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primary = (hose->first_busno == 0);
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pci_process_bridge_OF_ranges(hose, dev, primary);
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return 0;
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}
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void __init mv64x60_pci_init(void)
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{
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struct device_node *np = NULL;
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while ((np = of_find_compatible_node(np, "pci", "marvell,mv64x60-pci")))
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mv64x60_add_bridge(np);
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}
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