forked from luck/tmp_suning_uos_patched
mtd: onenand: remove s5pc100 related onenand codes
This patch removes s5pc100 related onenand codes because of no more support for S5PC100 SoC in mainline. Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -32,10 +32,10 @@ config MTD_ONENAND_OMAP2
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config MTD_ONENAND_SAMSUNG
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tristate "OneNAND on Samsung SOC controller support"
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depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4
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depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4
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help
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Support for a OneNAND flash device connected to an Samsung SOC.
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S3C64XX/S5PC100 use command mapping method.
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S3C64XX uses command mapping method.
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S5PC110/S5PC210 use generic OneNAND method.
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config MTD_ONENAND_OTP
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@ -10,7 +10,7 @@
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* published by the Free Software Foundation.
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*
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* Implementation:
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* S3C64XX and S5PC100: emulate the pseudo BufferRAM
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* S3C64XX: emulate the pseudo BufferRAM
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* S5PC110: use DMA
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*/
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@ -32,7 +32,6 @@
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enum soc_type {
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TYPE_S3C6400,
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TYPE_S3C6410,
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TYPE_S5PC100,
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TYPE_S5PC110,
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};
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@ -59,7 +58,6 @@ enum soc_type {
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#define MAP_11 (0x3)
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#define S3C64XX_CMD_MAP_SHIFT 24
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#define S5PC100_CMD_MAP_SHIFT 26
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#define S3C6400_FBA_SHIFT 10
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#define S3C6400_FPA_SHIFT 4
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@ -69,10 +67,6 @@ enum soc_type {
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#define S3C6410_FPA_SHIFT 6
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#define S3C6410_FSA_SHIFT 4
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#define S5PC100_FBA_SHIFT 13
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#define S5PC100_FPA_SHIFT 7
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#define S5PC100_FSA_SHIFT 5
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/* S5PC110 specific definitions */
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#define S5PC110_DMA_SRC_ADDR 0x400
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#define S5PC110_DMA_SRC_CFG 0x404
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@ -195,11 +189,6 @@ static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
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return (type << S3C64XX_CMD_MAP_SHIFT) | val;
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}
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static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
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{
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return (type << S5PC100_CMD_MAP_SHIFT) | val;
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}
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static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
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{
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return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
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@ -212,12 +201,6 @@ static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
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(fsa << S3C6410_FSA_SHIFT);
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}
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static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa)
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{
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return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) |
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(fsa << S5PC100_FSA_SHIFT);
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}
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static void s3c_onenand_reset(void)
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{
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unsigned long timeout = 0x10000;
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@ -835,9 +818,6 @@ static void s3c_onenand_setup(struct mtd_info *mtd)
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} else if (onenand->type == TYPE_S3C6410) {
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onenand->mem_addr = s3c6410_mem_addr;
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onenand->cmd_map = s3c64xx_cmd_map;
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} else if (onenand->type == TYPE_S5PC100) {
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onenand->mem_addr = s5pc100_mem_addr;
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onenand->cmd_map = s5pc1xx_cmd_map;
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} else if (onenand->type == TYPE_S5PC110) {
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/* Use generic onenand functions */
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this->read_bufferram = s5pc110_read_bufferram;
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@ -1110,9 +1090,6 @@ static struct platform_device_id s3c_onenand_driver_ids[] = {
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}, {
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.name = "s3c6410-onenand",
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.driver_data = TYPE_S3C6410,
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}, {
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.name = "s5pc100-onenand",
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.driver_data = TYPE_S5PC100,
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}, {
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.name = "s5pc110-onenand",
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.driver_data = TYPE_S5PC110,
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