AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

mmc: dw_mmc: correct the calculation for CLKDIV

Browse Source 
In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Seungwon Jeon 2012-05-22 13:01:21 +09:00 committed by Chris Ball
parent fda5f73686
commit e419990b5e
1 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/mmc/host/dw_mmc.c
View File

@ -617,14 +617,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
u32 div;
if (slot->clock != host->current_speed) {
if (host->bus_hz % slot->clock)
div = host->bus_hz / slot->clock;
if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
/*
* move the + 1 after the divide to prevent
* over-clocking the card.
*/
div = ((host->bus_hz / slot->clock) >> 1) + 1;
else
div = (host->bus_hz / slot->clock) >> 1;
div += 1;
div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
dev_info(&slot->mmc->class_dev,
"Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"