forked from luck/tmp_suning_uos_patched
soc/tegra: pmc: Query PCLK clock rate at probe time
It is possible to get a lockup if kernel decides to enter LP2 cpuidle from some clk-notifier, in that case CCF's "prepare" mutex is kept locked and thus clk_get_rate(pclk) blocks on the same mutex with interrupts being disabled, hanging machine. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -324,6 +324,7 @@ static const char * const tegra210_reset_sources[] = {
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* @pctl_dev: pin controller exposed by the PMC
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* @domain: IRQ domain provided by the PMC
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* @irq: chip implementation for the IRQ domain
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* @clk_nb: pclk clock changes handler
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*/
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struct tegra_pmc {
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struct device *dev;
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@ -359,6 +360,8 @@ struct tegra_pmc {
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struct irq_domain *domain;
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struct irq_chip irq;
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struct notifier_block clk_nb;
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};
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static struct tegra_pmc *pmc = &(struct tegra_pmc) {
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@ -1207,7 +1210,7 @@ static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
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return err;
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if (pmc->clk) {
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rate = clk_get_rate(pmc->clk);
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rate = pmc->rate;
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if (!rate) {
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dev_err(pmc->dev, "failed to get clock rate\n");
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return -ENODEV;
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@ -1448,6 +1451,7 @@ void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
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void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
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{
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unsigned long long rate = 0;
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u64 ticks;
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u32 value;
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switch (mode) {
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@ -1456,7 +1460,7 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
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break;
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case TEGRA_SUSPEND_LP2:
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rate = clk_get_rate(pmc->clk);
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rate = pmc->rate;
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break;
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default:
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@ -1466,21 +1470,15 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
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if (WARN_ON_ONCE(rate == 0))
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rate = 100000000;
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if (rate != pmc->rate) {
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u64 ticks;
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ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
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do_div(ticks, USEC_PER_SEC);
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tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
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ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
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do_div(ticks, USEC_PER_SEC);
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tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
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ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
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do_div(ticks, USEC_PER_SEC);
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tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
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ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
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do_div(ticks, USEC_PER_SEC);
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tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
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wmb();
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pmc->rate = rate;
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}
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wmb();
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value = tegra_pmc_readl(pmc, PMC_CNTRL);
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value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
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@ -2140,6 +2138,33 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
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return 0;
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}
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static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
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unsigned long action, void *ptr)
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{
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struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
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struct clk_notifier_data *data = ptr;
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switch (action) {
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case PRE_RATE_CHANGE:
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mutex_lock(&pmc->powergates_lock);
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break;
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case POST_RATE_CHANGE:
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pmc->rate = data->new_rate;
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/* fall through */
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case ABORT_RATE_CHANGE:
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mutex_unlock(&pmc->powergates_lock);
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break;
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default:
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WARN_ON_ONCE(1);
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return notifier_from_errno(-EINVAL);
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}
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return NOTIFY_OK;
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}
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static int tegra_pmc_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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@ -2203,6 +2228,23 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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pmc->clk = NULL;
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}
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/*
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* PCLK clock rate can't be retrieved using CLK API because it
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* causes lockup if CPU enters LP2 idle state from some other
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* CLK notifier, hence we're caching the rate's value locally.
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*/
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if (pmc->clk) {
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pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
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err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
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if (err) {
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dev_err(&pdev->dev,
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"failed to register clk notifier\n");
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return err;
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}
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pmc->rate = clk_get_rate(pmc->clk);
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}
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pmc->dev = &pdev->dev;
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tegra_pmc_init(pmc);
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@ -2254,6 +2296,8 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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cleanup_sysfs:
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device_remove_file(&pdev->dev, &dev_attr_reset_reason);
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device_remove_file(&pdev->dev, &dev_attr_reset_level);
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clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
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return err;
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}
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