forked from luck/tmp_suning_uos_patched
firewire: ohci: do not clear PHY interrupt status inadvertently
The interrupt status bits in PHY register 5 are cleared by writing a one bit. To avoid clearing them unadvertently, do not write them back when they were read as set, but only when they have been explicitly requested to be set. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
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@ -28,6 +28,7 @@ struct fw_packet;
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#define PHY_CONTENDER 0x40
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#define PHY_BUS_RESET 0x40
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#define PHY_BUS_SHORT_RESET 0x40
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#define PHY_INT_STATUS_BITS 0x3c
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#define BANDWIDTH_AVAILABLE_INITIAL 4915
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#define BROADCAST_CHANNEL_INITIAL (1 << 31 | 31)
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@ -490,6 +490,13 @@ static int ohci_update_phy_reg(struct fw_card *card, int addr,
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if (err < 0)
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return err;
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/*
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* The interrupt status bits are cleared by writing a one bit.
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* Avoid clearing them unless explicitly requested in set_bits.
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*/
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if (addr == 5)
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clear_bits |= PHY_INT_STATUS_BITS;
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old = (old & ~clear_bits) | set_bits;
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reg_write(ohci, OHCI1394_PhyControl,
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OHCI1394_PhyControl_Write(addr, old));
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