forked from luck/tmp_suning_uos_patched
iwlagn: queue frames according to context
Frames for different contexts need to be put on different queues, and multicast after DTIM frames have a special queue yet which also depends on the context, so put all this into the context. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
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parent
60744f6297
commit
e72f368be6
@ -71,18 +71,6 @@ static const u8 tid_to_ac[] = {
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2, 3, 3, 2, 1, 1, 0, 0
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};
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static const u8 ac_to_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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};
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static inline int get_fifo_from_ac(u8 ac)
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{
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return ac_to_fifo[ac];
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}
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static inline int get_ac_from_tid(u16 tid)
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{
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if (likely(tid < ARRAY_SIZE(tid_to_ac)))
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@ -92,10 +80,10 @@ static inline int get_ac_from_tid(u16 tid)
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return -EINVAL;
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}
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static inline int get_fifo_from_tid(u16 tid)
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static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
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{
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if (likely(tid < ARRAY_SIZE(tid_to_ac)))
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return get_fifo_from_ac(tid_to_ac[tid]);
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return ctx->ac_to_fifo[tid_to_ac[tid]];
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/* no support for TIDs 8-15 yet */
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return -EINVAL;
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@ -333,11 +321,6 @@ void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
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iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
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}
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static inline int get_queue_from_ac(u16 ac)
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{
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return ac;
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}
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/*
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* handle build REPLY_TX command notification.
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*/
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@ -595,7 +578,20 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
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iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
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}
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txq_id = get_queue_from_ac(skb_get_queue_mapping(skb));
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/*
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* Send this frame after DTIM -- there's a special queue
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* reserved for this for contexts that support AP mode.
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*/
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if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
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txq_id = ctx->mcast_queue;
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/*
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* The microcode will clear the more data
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* bit in the last frame it transmits.
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*/
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hdr->frame_control |=
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cpu_to_le16(IEEE80211_FCTL_MOREDATA);
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} else
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txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
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/* irqs already disabled/saved above when locking priv->lock */
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spin_lock(&priv->sta_lock);
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@ -984,7 +980,7 @@ int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
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unsigned long flags;
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struct iwl_tid_data *tid_data;
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tx_fifo = get_fifo_from_tid(tid);
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tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
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if (unlikely(tx_fifo < 0))
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return tx_fifo;
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@ -1045,7 +1041,7 @@ int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
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int write_ptr, read_ptr;
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unsigned long flags;
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tx_fifo_id = get_fifo_from_tid(tid);
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tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
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if (unlikely(tx_fifo_id < 0))
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return tx_fifo_id;
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@ -1133,7 +1129,7 @@ int iwlagn_txq_check_empty(struct iwl_priv *priv,
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if ((txq_id == tid_data->agg.txq_id) &&
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(q->read_ptr == q->write_ptr)) {
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u16 ssn = SEQ_TO_SN(tid_data->seq_number);
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int tx_fifo = get_fifo_from_tid(tid);
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int tx_fifo = get_fifo_from_tid(ctx, tid);
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IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
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priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
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ssn, tx_fifo);
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@ -4196,6 +4196,28 @@ static int iwl_set_hw_params(struct iwl_priv *priv)
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return priv->cfg->ops->lib->set_hw_params(priv);
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}
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static const u8 iwlagn_bss_ac_to_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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};
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static const u8 iwlagn_bss_ac_to_queue[] = {
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0, 1, 2, 3,
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};
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static const u8 iwlagn_pan_ac_to_fifo[] = {
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IWL_TX_FIFO_VO_IPAN,
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IWL_TX_FIFO_VI_IPAN,
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IWL_TX_FIFO_BE_IPAN,
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IWL_TX_FIFO_BK_IPAN,
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};
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static const u8 iwlagn_pan_ac_to_queue[] = {
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7, 6, 5, 4,
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};
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static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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int err = 0, i;
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@ -4242,6 +4264,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
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priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
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priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
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priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
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priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
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priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
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priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
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@ -4251,6 +4275,9 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
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priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
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priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
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priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
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priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
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priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
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BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
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@ -1111,6 +1111,11 @@ enum iwl_rxon_context_id {
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struct iwl_rxon_context {
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struct ieee80211_vif *vif;
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const u8 *ac_to_fifo;
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const u8 *ac_to_queue;
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u8 mcast_queue;
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enum iwl_rxon_context_id ctxid;
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/*
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* We declare this const so it can only be
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