forked from luck/tmp_suning_uos_patched
[MIPS] Remove asm-mips/mips-boards/atlas{,int}.h
asm-mips/mips-boards/atlas{,int}.h are now obsolete.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Adrian Bunk
Ralf Baechle
parent
fc22c3571c
commit
e76812eddc
@ -1,80 +0,0 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Defines of the Atlas board specific address-MAP, registers, etc.
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*
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*/
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#ifndef _MIPS_ATLAS_H
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#define _MIPS_ATLAS_H
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#include <asm/addrspace.h>
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/*
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* Atlas RTC-device indirect register access.
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*/
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#define ATLAS_RTC_ADR_REG 0x1f000800
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#define ATLAS_RTC_DAT_REG 0x1f000808
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/*
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* Atlas interrupt controller register base.
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*/
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#define ATLAS_ICTRL_REGS_BASE 0x1f000000
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/*
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* Atlas registers are memory mapped on 64-bit aligned boundaries and
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* only word access are allowed.
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*/
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struct atlas_ictrl_regs {
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volatile unsigned int intraw;
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int dummy1;
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volatile unsigned int intseten;
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int dummy2;
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volatile unsigned int intrsten;
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int dummy3;
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volatile unsigned int intenable;
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int dummy4;
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volatile unsigned int intstatus;
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int dummy5;
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};
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/*
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* Atlas UART register base.
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*/
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#define ATLAS_UART_REGS_BASE 0x1f000900
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#define ATLAS_BASE_BAUD ( 3686400 / 16 )
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/*
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* Atlas PSU standby register.
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*/
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#define ATLAS_PSUSTBY_REG 0x1f000600
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#define ATLAS_GOSTBY 0x4d
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/*
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* We make a universal assumption about the way the bootloader (YAMON)
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* have located the Philips SAA9730 chip.
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* This is not ideal, but is needed for setting up remote debugging as
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* soon as possible.
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*/
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#define ATLAS_SAA9730_REG 0x10800000
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#define ATLAS_SAA9730_BAUDCLOCK 3692300
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#endif /* !(_MIPS_ATLAS_H) */
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@ -1,109 +0,0 @@
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/*
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* Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Defines for the Atlas interrupt controller.
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*
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*/
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#ifndef _MIPS_ATLASINT_H
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#define _MIPS_ATLASINT_H
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#include <irq.h>
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/* CPU interrupt offsets */
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#define MIPSCPU_INT_SW0 0
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#define MIPSCPU_INT_SW1 1
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#define MIPSCPU_INT_MB0 2
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#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0
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#define MIPSCPU_INT_MB1 3
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#define MIPSCPU_INT_MB2 4
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#define MIPSCPU_INT_MB3 5
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#define MIPSCPU_INT_MB4 6
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/*
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* Interrupts 8..39 are used for Atlas interrupt controller interrupts
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*/
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#define ATLAS_INT_BASE 8
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#define ATLAS_INT_UART (ATLAS_INT_BASE + 0)
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#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1)
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#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2)
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#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3)
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#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4)
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#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5)
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#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6)
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#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7)
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#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8)
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#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9)
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#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10)
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#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11)
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#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12)
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#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13)
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#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14)
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#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15)
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#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16)
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#define ATLAS_INT_ETH ATLAS_INT_INTB
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#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17)
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#define ATLAS_INT_SCSI ATLAS_INT_INTC
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#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18)
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#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19)
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#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20)
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#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21)
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#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22)
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#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23)
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#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24)
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#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25)
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#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26)
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#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27)
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#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28)
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#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29)
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#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30)
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#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31)
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#define ATLAS_INT_END (ATLAS_INT_BASE + 31)
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/*
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* Interrupts 64..127 are used for Soc-it Classic interrupts
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*/
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#define MSC01C_INT_BASE 64
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/* SOC-it Classic interrupt offsets */
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#define MSC01C_INT_TMR 0
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#define MSC01C_INT_PCI 1
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/*
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* Interrupts 64..127 are used for Soc-it EIC interrupts
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*/
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#define MSC01E_INT_BASE 64
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/* SOC-it EIC interrupt offsets */
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#define MSC01E_INT_SW0 1
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#define MSC01E_INT_SW1 2
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#define MSC01E_INT_MB0 3
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#define MSC01E_INT_ATLAS MSC01E_INT_MB0
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#define MSC01E_INT_MB1 4
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#define MSC01E_INT_MB2 5
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#define MSC01E_INT_MB3 6
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#define MSC01E_INT_MB4 7
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#define MSC01E_INT_TMR 8
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#define MSC01E_INT_PCI 9
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#define MSC01E_INT_PERFCTR 10
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#define MSC01E_INT_CPUCTR 11
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#endif /* !(_MIPS_ATLASINT_H) */
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