forked from luck/tmp_suning_uos_patched
pinctrl: aspeed-g6: Fix LPC/eSPI mux configuration
Early revisions of the AST2600 datasheet are conflicted about the state
of the LPC/eSPI strapping bit (SCU510[6]). Conversations with ASPEED
determined that the reference pinmux configuration tables were in error
and the SCU documentation contained the correct configuration. Update
the driver to reflect the state described in the SCU documentation.
Fixes: 2eda1cdec4
("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191202050110.15340-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
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e42617b825
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eb45f2110b
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@ -1088,60 +1088,52 @@ SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15));
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#define AB7 176
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SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16));
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PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0);
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#define AB8 177
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SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17));
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PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1);
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#define AC8 178
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SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18));
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PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2);
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#define AC7 179
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SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19));
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PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3);
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#define AE7 180
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SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20));
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PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK);
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#define AF7 181
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SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21));
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PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS);
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#define AD7 182
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SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22));
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PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT);
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FUNC_GROUP_DECL(LSIRQ, AD7);
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FUNC_GROUP_DECL(ESPIALT, AD7);
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#define AD8 183
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SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23),
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SIG_DESC_CLEAR(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23),
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SIG_DESC_SET(SCU510, 6));
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SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23));
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PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST);
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FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
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