forked from luck/tmp_suning_uos_patched
iommu/amd: Fix race in increase_address_space()/fetch_pte()
The 'pt_root' and 'mode' struct members of 'struct protection_domain'
need to be get/set atomically, otherwise the page-table of the domain
can get corrupted.
Merge the fields into one atomic64_t struct member which can be
get/set atomically.
Fixes: 92d420ec02 ("iommu/amd: Relax locking in dma_ops path")
Reported-by: Qian Cai <cai@lca.pw>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Tested-by: Qian Cai <cai@lca.pw>
Link: https://lore.kernel.org/r/20200504125413.16798-2-joro@8bytes.org
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Joerg Roedel
parent
0e698dfa28
commit
eb791aa70b
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@ -151,6 +151,26 @@ static struct protection_domain *to_pdomain(struct iommu_domain *dom)
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return container_of(dom, struct protection_domain, domain);
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}
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static void amd_iommu_domain_get_pgtable(struct protection_domain *domain,
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struct domain_pgtable *pgtable)
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{
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u64 pt_root = atomic64_read(&domain->pt_root);
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pgtable->root = (u64 *)(pt_root & PAGE_MASK);
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pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */
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}
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static u64 amd_iommu_domain_encode_pgtable(u64 *root, int mode)
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{
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u64 pt_root;
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/* lowest 3 bits encode pgtable mode */
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pt_root = mode & 7;
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pt_root |= (u64)root;
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return pt_root;
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}
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static struct iommu_dev_data *alloc_dev_data(u16 devid)
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{
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struct iommu_dev_data *dev_data;
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@ -1397,13 +1417,18 @@ static struct page *free_sub_pt(unsigned long root, int mode,
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static void free_pagetable(struct protection_domain *domain)
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{
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unsigned long root = (unsigned long)domain->pt_root;
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struct domain_pgtable pgtable;
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struct page *freelist = NULL;
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unsigned long root;
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BUG_ON(domain->mode < PAGE_MODE_NONE ||
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domain->mode > PAGE_MODE_6_LEVEL);
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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atomic64_set(&domain->pt_root, 0);
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freelist = free_sub_pt(root, domain->mode, freelist);
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BUG_ON(pgtable.mode < PAGE_MODE_NONE ||
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pgtable.mode > PAGE_MODE_6_LEVEL);
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root = (unsigned long)pgtable.root;
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freelist = free_sub_pt(root, pgtable.mode, freelist);
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free_page_list(freelist);
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}
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@ -1417,24 +1442,28 @@ static bool increase_address_space(struct protection_domain *domain,
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unsigned long address,
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gfp_t gfp)
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{
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struct domain_pgtable pgtable;
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unsigned long flags;
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bool ret = false;
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u64 *pte;
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u64 *pte, root;
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spin_lock_irqsave(&domain->lock, flags);
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if (address <= PM_LEVEL_SIZE(domain->mode) ||
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WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (address <= PM_LEVEL_SIZE(pgtable.mode) ||
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WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL))
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goto out;
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pte = (void *)get_zeroed_page(gfp);
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if (!pte)
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goto out;
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*pte = PM_LEVEL_PDE(domain->mode,
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iommu_virt_to_phys(domain->pt_root));
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domain->pt_root = pte;
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domain->mode += 1;
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*pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root));
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root = amd_iommu_domain_encode_pgtable(pte, pgtable.mode + 1);
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atomic64_set(&domain->pt_root, root);
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ret = true;
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@ -1451,16 +1480,22 @@ static u64 *alloc_pte(struct protection_domain *domain,
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gfp_t gfp,
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bool *updated)
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{
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struct domain_pgtable pgtable;
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int level, end_lvl;
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u64 *pte, *page;
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BUG_ON(!is_power_of_2(page_size));
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while (address > PM_LEVEL_SIZE(domain->mode))
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*updated = increase_address_space(domain, address, gfp) || *updated;
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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level = domain->mode - 1;
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pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
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while (address > PM_LEVEL_SIZE(pgtable.mode)) {
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*updated = increase_address_space(domain, address, gfp) || *updated;
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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}
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level = pgtable.mode - 1;
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pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
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address = PAGE_SIZE_ALIGN(address, page_size);
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end_lvl = PAGE_SIZE_LEVEL(page_size);
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@ -1536,16 +1571,19 @@ static u64 *fetch_pte(struct protection_domain *domain,
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unsigned long address,
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unsigned long *page_size)
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{
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struct domain_pgtable pgtable;
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int level;
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u64 *pte;
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*page_size = 0;
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if (address > PM_LEVEL_SIZE(domain->mode))
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (address > PM_LEVEL_SIZE(pgtable.mode))
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return NULL;
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level = domain->mode - 1;
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pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
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level = pgtable.mode - 1;
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pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
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*page_size = PTE_LEVEL_PAGE_SIZE(level);
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while (level > 0) {
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@ -1806,6 +1844,7 @@ static void dma_ops_domain_free(struct protection_domain *domain)
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static struct protection_domain *dma_ops_domain_alloc(void)
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{
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struct protection_domain *domain;
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u64 *pt_root, root;
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domain = kzalloc(sizeof(struct protection_domain), GFP_KERNEL);
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if (!domain)
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@ -1814,12 +1853,14 @@ static struct protection_domain *dma_ops_domain_alloc(void)
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if (protection_domain_init(domain))
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goto free_domain;
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domain->mode = PAGE_MODE_3_LEVEL;
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domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
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domain->flags = PD_DMA_OPS_MASK;
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if (!domain->pt_root)
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pt_root = (void *)get_zeroed_page(GFP_KERNEL);
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if (!pt_root)
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goto free_domain;
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root = amd_iommu_domain_encode_pgtable(pt_root, PAGE_MODE_3_LEVEL);
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atomic64_set(&domain->pt_root, root);
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domain->flags = PD_DMA_OPS_MASK;
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if (iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
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goto free_domain;
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@ -1843,14 +1884,17 @@ static bool dma_ops_domain(struct protection_domain *domain)
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static void set_dte_entry(u16 devid, struct protection_domain *domain,
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bool ats, bool ppr)
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{
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struct domain_pgtable pgtable;
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u64 pte_root = 0;
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u64 flags = 0;
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u32 old_domid;
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if (domain->mode != PAGE_MODE_NONE)
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pte_root = iommu_virt_to_phys(domain->pt_root);
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
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if (pgtable.mode != PAGE_MODE_NONE)
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pte_root = iommu_virt_to_phys(pgtable.root);
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pte_root |= (pgtable.mode & DEV_ENTRY_MODE_MASK)
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<< DEV_ENTRY_MODE_SHIFT;
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pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
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@ -2375,6 +2419,7 @@ static struct protection_domain *protection_domain_alloc(void)
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static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
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{
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struct protection_domain *pdomain;
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u64 *pt_root, root;
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switch (type) {
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case IOMMU_DOMAIN_UNMANAGED:
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@ -2382,13 +2427,15 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
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if (!pdomain)
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return NULL;
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pdomain->mode = PAGE_MODE_3_LEVEL;
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pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
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if (!pdomain->pt_root) {
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pt_root = (void *)get_zeroed_page(GFP_KERNEL);
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if (!pt_root) {
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protection_domain_free(pdomain);
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return NULL;
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}
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root = amd_iommu_domain_encode_pgtable(pt_root, PAGE_MODE_3_LEVEL);
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atomic64_set(&pdomain->pt_root, root);
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pdomain->domain.geometry.aperture_start = 0;
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pdomain->domain.geometry.aperture_end = ~0ULL;
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pdomain->domain.geometry.force_aperture = true;
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@ -2406,7 +2453,7 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
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if (!pdomain)
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return NULL;
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pdomain->mode = PAGE_MODE_NONE;
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atomic64_set(&pdomain->pt_root, PAGE_MODE_NONE);
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break;
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default:
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return NULL;
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@ -2418,6 +2465,7 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
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static void amd_iommu_domain_free(struct iommu_domain *dom)
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{
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struct protection_domain *domain;
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struct domain_pgtable pgtable;
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domain = to_pdomain(dom);
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@ -2435,7 +2483,9 @@ static void amd_iommu_domain_free(struct iommu_domain *dom)
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dma_ops_domain_free(domain);
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break;
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default:
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if (domain->mode != PAGE_MODE_NONE)
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (pgtable.mode != PAGE_MODE_NONE)
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free_pagetable(domain);
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if (domain->flags & PD_IOMMUV2_MASK)
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@ -2518,10 +2568,12 @@ static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
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gfp_t gfp)
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{
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struct protection_domain *domain = to_pdomain(dom);
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struct domain_pgtable pgtable;
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int prot = 0;
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int ret;
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if (domain->mode == PAGE_MODE_NONE)
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (pgtable.mode == PAGE_MODE_NONE)
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return -EINVAL;
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if (iommu_prot & IOMMU_READ)
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@ -2541,8 +2593,10 @@ static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
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struct iommu_iotlb_gather *gather)
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{
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struct protection_domain *domain = to_pdomain(dom);
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struct domain_pgtable pgtable;
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if (domain->mode == PAGE_MODE_NONE)
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (pgtable.mode == PAGE_MODE_NONE)
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return 0;
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return iommu_unmap_page(domain, iova, page_size);
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@ -2553,9 +2607,11 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
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{
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struct protection_domain *domain = to_pdomain(dom);
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unsigned long offset_mask, pte_pgsize;
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struct domain_pgtable pgtable;
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u64 *pte, __pte;
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if (domain->mode == PAGE_MODE_NONE)
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (pgtable.mode == PAGE_MODE_NONE)
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return iova;
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pte = fetch_pte(domain, iova, &pte_pgsize);
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@ -2708,16 +2764,26 @@ EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
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void amd_iommu_domain_direct_map(struct iommu_domain *dom)
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{
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struct protection_domain *domain = to_pdomain(dom);
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struct domain_pgtable pgtable;
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unsigned long flags;
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u64 pt_root;
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spin_lock_irqsave(&domain->lock, flags);
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/* First save pgtable configuration*/
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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/* Update data structure */
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domain->mode = PAGE_MODE_NONE;
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pt_root = amd_iommu_domain_encode_pgtable(NULL, PAGE_MODE_NONE);
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atomic64_set(&domain->pt_root, pt_root);
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/* Make changes visible to IOMMUs */
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update_domain(domain);
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/* Restore old pgtable in domain->ptroot to free page-table */
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pt_root = amd_iommu_domain_encode_pgtable(pgtable.root, pgtable.mode);
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atomic64_set(&domain->pt_root, pt_root);
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/* Page-table is not visible to IOMMU anymore, so free it */
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free_pagetable(domain);
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@ -2908,9 +2974,11 @@ static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
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static int __set_gcr3(struct protection_domain *domain, int pasid,
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unsigned long cr3)
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{
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struct domain_pgtable pgtable;
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u64 *pte;
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if (domain->mode != PAGE_MODE_NONE)
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (pgtable.mode != PAGE_MODE_NONE)
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return -EINVAL;
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pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
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@ -2924,9 +2992,11 @@ static int __set_gcr3(struct protection_domain *domain, int pasid,
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static int __clear_gcr3(struct protection_domain *domain, int pasid)
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{
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struct domain_pgtable pgtable;
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u64 *pte;
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if (domain->mode != PAGE_MODE_NONE)
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amd_iommu_domain_get_pgtable(domain, &pgtable);
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if (pgtable.mode != PAGE_MODE_NONE)
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return -EINVAL;
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pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
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@ -468,8 +468,7 @@ struct protection_domain {
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iommu core code */
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spinlock_t lock; /* mostly used to lock the page table*/
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u16 id; /* the domain id written to the device table */
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int mode; /* paging mode (0-6 levels) */
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u64 *pt_root; /* page table root pointer */
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atomic64_t pt_root; /* pgtable root and pgtable mode */
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int glx; /* Number of levels for GCR3 table */
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u64 *gcr3_tbl; /* Guest CR3 table */
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unsigned long flags; /* flags to find out type of domain */
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@ -477,6 +476,12 @@ struct protection_domain {
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unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
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};
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/* For decocded pt_root */
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struct domain_pgtable {
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int mode;
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u64 *root;
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};
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/*
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* Structure where we save information about one hardware AMD IOMMU in the
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* system.
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