forked from luck/tmp_suning_uos_patched
ARM i.MX3: Make ccm base address a variable
Instead of having a cpu_is_* in each ccm register access it is more efficient to make it a variable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -24,48 +24,47 @@
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#define CKIH_CLK_FREQ_27MHZ 27000000
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#define CKIH_CLK_FREQ_27MHZ 27000000
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#define CKIL_CLK_FREQ 32768
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#define CKIL_CLK_FREQ 32768
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#define MXC_CCM_BASE (cpu_is_mx31() ? \
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extern void __iomem *mx3_ccm_base;
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MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR))
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/* Register addresses */
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/* Register addresses */
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#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
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#define MXC_CCM_CCMR 0x00
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#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04)
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#define MXC_CCM_PDR0 0x04
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#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08)
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#define MXC_CCM_PDR1 0x08
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#define MX35_CCM_PDR2 (MXC_CCM_BASE + 0x0C)
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#define MX35_CCM_PDR2 0x0C
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#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C)
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#define MXC_CCM_RCSR 0x0C
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#define MX35_CCM_PDR3 (MXC_CCM_BASE + 0x10)
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#define MX35_CCM_PDR3 0x10
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#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10)
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#define MXC_CCM_MPCTL 0x10
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#define MX35_CCM_PDR4 (MXC_CCM_BASE + 0x14)
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#define MX35_CCM_PDR4 0x14
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#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14)
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#define MXC_CCM_UPCTL 0x14
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#define MX35_CCM_RCSR (MXC_CCM_BASE + 0x18)
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#define MX35_CCM_RCSR 0x18
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#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18)
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#define MXC_CCM_SRPCTL 0x18
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#define MX35_CCM_MPCTL (MXC_CCM_BASE + 0x1C)
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#define MX35_CCM_MPCTL 0x1C
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#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C)
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#define MXC_CCM_COSR 0x1C
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#define MX35_CCM_PPCTL (MXC_CCM_BASE + 0x20)
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#define MX35_CCM_PPCTL 0x20
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#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20)
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#define MXC_CCM_CGR0 0x20
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#define MX35_CCM_ACMR (MXC_CCM_BASE + 0x24)
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#define MX35_CCM_ACMR 0x24
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#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24)
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#define MXC_CCM_CGR1 0x24
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#define MX35_CCM_COSR (MXC_CCM_BASE + 0x28)
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#define MX35_CCM_COSR 0x28
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#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28)
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#define MXC_CCM_CGR2 0x28
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#define MX35_CCM_CGR0 (MXC_CCM_BASE + 0x2C)
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#define MX35_CCM_CGR0 0x2C
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#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C)
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#define MXC_CCM_WIMR 0x2C
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#define MX35_CCM_CGR1 (MXC_CCM_BASE + 0x30)
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#define MX35_CCM_CGR1 0x30
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#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30)
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#define MXC_CCM_LDC 0x30
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#define MX35_CCM_CGR2 (MXC_CCM_BASE + 0x34)
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#define MX35_CCM_CGR2 0x34
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#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34)
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#define MXC_CCM_DCVR0 0x34
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#define MX35_CCM_CGR3 (MXC_CCM_BASE + 0x38)
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#define MX35_CCM_CGR3 0x38
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#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38)
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#define MXC_CCM_DCVR1 0x38
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#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C)
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#define MXC_CCM_DCVR2 0x3C
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#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40)
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#define MXC_CCM_DCVR3 0x40
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#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44)
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#define MXC_CCM_LTR0 0x44
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#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48)
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#define MXC_CCM_LTR1 0x48
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#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C)
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#define MXC_CCM_LTR2 0x4C
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#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50)
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#define MXC_CCM_LTR3 0x50
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#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54)
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#define MXC_CCM_LTBR0 0x54
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#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58)
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#define MXC_CCM_LTBR1 0x58
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#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C)
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#define MXC_CCM_PMCR0 0x5C
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#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60)
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#define MXC_CCM_PMCR1 0x60
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#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64)
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#define MXC_CCM_PDR2 0x64
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/* Register bit definitions */
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/* Register bit definitions */
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#define MXC_CCM_CCMR_WBEN (1 << 27)
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#define MXC_CCM_CCMR_WBEN (1 << 27)
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@ -31,6 +31,10 @@
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#include <mach/iomux-v3.h>
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#include <mach/iomux-v3.h>
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#include <mach/irqs.h>
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#include <mach/irqs.h>
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#include "crmregs-imx3.h"
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void __iomem *mx3_ccm_base;
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static void imx3_idle(void)
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static void imx3_idle(void)
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{
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{
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unsigned long reg = 0;
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unsigned long reg = 0;
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@ -137,6 +141,7 @@ void __init imx31_init_early(void)
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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arch_ioremap_caller = imx3_ioremap_caller;
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arch_ioremap_caller = imx3_ioremap_caller;
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arm_pm_idle = imx3_idle;
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arm_pm_idle = imx3_idle;
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mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
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}
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}
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void __init mx31_init_irq(void)
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void __init mx31_init_irq(void)
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@ -210,6 +215,7 @@ void __init imx35_init_early(void)
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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arm_pm_idle = imx3_idle;
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arm_pm_idle = imx3_idle;
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arch_ioremap_caller = imx3_ioremap_caller;
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arch_ioremap_caller = imx3_ioremap_caller;
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mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
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}
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}
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void __init mx35_init_irq(void)
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void __init mx35_init_irq(void)
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@ -21,14 +21,14 @@
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*/
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*/
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void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
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void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
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{
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{
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int reg = __raw_readl(MXC_CCM_CCMR);
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int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_LPM_MASK;
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reg &= ~MXC_CCM_CCMR_LPM_MASK;
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switch (mode) {
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switch (mode) {
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case MX3_WAIT:
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case MX3_WAIT:
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if (cpu_is_mx35())
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if (cpu_is_mx35())
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reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
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reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
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__raw_writel(reg, MXC_CCM_CCMR);
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__raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
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break;
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break;
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default:
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default:
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pr_err("Unknown cpu power mode: %d\n", mode);
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pr_err("Unknown cpu power mode: %d\n", mode);
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