forked from luck/tmp_suning_uos_patched
[PATCH] Move iSeries and common vectors into unused space in head.S
In the ppc64 kernel head.S there is currently quite a lot of unused space between the naca (at fixed address 0x4000) and the fwnmi data area (at fixed address 0x7000). This patch moves various exception vectors and support code into this region to use the wasted space. The functions load_up_fpu and load_up_altivec are moved down as well, since they are essentially continuations of the fp_unavailable_common and altivec_unavailable_common vectors, respectively. Likewise, the fwnmi vectors themselves are moved down into this area, because while the location of the fwnmi data area is fixed by the RPA, the vectors themselves can be anywhere sufficiently low. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson
Paul Mackerras
parent
2e2446ea07
commit
ec465515ee
@ -52,9 +52,8 @@
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* We layout physical memory as follows:
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* 0x0000 - 0x00ff : Secondary processor spin code
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* 0x0100 - 0x2fff : pSeries Interrupt prologs
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* 0x3000 - 0x3fff : Interrupt support
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* 0x4000 - 0x4fff : NACA
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* 0x6000 : iSeries and common interrupt prologs
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* 0x3000 - 0x6fff : interrupt support, iSeries and common interrupt prologs
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* 0x7000 - 0x7fff : FWNMI data area
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* 0x9000 - 0x9fff : Initial segment table
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*/
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@ -501,17 +500,35 @@ system_call_pSeries:
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STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
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STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
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/* moved from 0xf00 */
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STD_EXCEPTION_PSERIES(0x3000, performance_monitor)
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. = 0x3000
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. = 0x3100
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/*** pSeries interrupt support ***/
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/* moved from 0xf00 */
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STD_EXCEPTION_PSERIES(., performance_monitor)
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.align 7
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_GLOBAL(do_stab_bolted_pSeries)
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mtcrf 0x80,r12
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mfspr r12,SPRG2
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EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
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/*
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* Vectors for the FWNMI option. Share common code.
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*/
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.globl system_reset_fwnmi
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system_reset_fwnmi:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
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. = 0x6100
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.globl machine_check_fwnmi
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machine_check_fwnmi:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
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#ifdef CONFIG_PPC_ISERIES
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/*** ISeries-LPAR interrupt handlers ***/
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@ -656,51 +673,8 @@ hardware_interrupt_iSeries_masked:
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ld r13,PACA_EXGEN+EX_R13(r13)
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rfid
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b . /* prevent speculative execution */
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#endif
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/*
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* Data area reserved for FWNMI option.
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*/
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.= 0x7000
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.globl fwnmi_data_area
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fwnmi_data_area:
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#ifdef CONFIG_PPC_ISERIES
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. = LPARMAP_PHYS
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#include "lparmap.s"
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#endif /* CONFIG_PPC_ISERIES */
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/*
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* Vectors for the FWNMI option. Share common code.
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*/
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. = 0x8000
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.globl system_reset_fwnmi
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system_reset_fwnmi:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
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.globl machine_check_fwnmi
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machine_check_fwnmi:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
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/*
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* Space for the initial segment table
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* For LPAR, the hypervisor must fill in at least one entry
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* before we get control (with relocate on)
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*/
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. = STAB0_PHYS_ADDR
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.globl __start_stab
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__start_stab:
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. = (STAB0_PHYS_ADDR + PAGE_SIZE)
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.globl __end_stab
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__end_stab:
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/*** Common interrupt handlers ***/
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STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
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@ -891,6 +865,62 @@ fp_unavailable_common:
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bl .kernel_fp_unavailable_exception
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BUG_OPCODE
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/*
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* load_up_fpu(unused, unused, tsk)
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* Disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Enables the FPU for use in the kernel on return.
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* On SMP we know the fpu is free, since we give it up every
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* switch (ie, no lazy save of the FP registers).
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* On entry: r13 == 'current' && last_task_used_math != 'current'
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*/
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_STATIC(load_up_fpu)
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mfmsr r5 /* grab the current MSR */
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ori r5,r5,MSR_FP
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mtmsrd r5 /* enable use of fpu now */
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isync
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/*
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* For SMP, we don't do lazy FPU switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_fpu in switch_to.
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*
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*/
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#ifndef CONFIG_SMP
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ld r3,last_task_used_math@got(r2)
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ld r4,0(r3)
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cmpdi 0,r4,0
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beq 1f
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/* Save FP state to last_task_used_math's THREAD struct */
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addi r4,r4,THREAD
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SAVE_32FPRS(0, r4)
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mffs fr0
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stfd fr0,THREAD_FPSCR(r4)
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/* Disable FP for last_task_used_math */
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ld r5,PT_REGS(r4)
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ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r6,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r6
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std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* enable use of FP after return */
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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ld r4,THREAD_FPEXC_MODE(r5)
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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lfd fr0,THREAD_FPSCR(r5)
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mtfsf 0xff,fr0
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REST_32FPRS(0, r5)
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#ifndef CONFIG_SMP
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/* Update last_task_used_math to 'current' */
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subi r4,r5,THREAD /* Back to 'current' */
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std r4,0(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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b fast_exception_return
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.align 7
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.globl altivec_unavailable_common
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altivec_unavailable_common:
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@ -906,6 +936,80 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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bl .altivec_unavailable_exception
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b .ret_from_except
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#ifdef CONFIG_ALTIVEC
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/*
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* load_up_altivec(unused, unused, tsk)
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* Disable VMX for the task which had it previously,
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* and save its vector registers in its thread_struct.
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* Enables the VMX for use in the kernel on return.
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* On SMP we know the VMX is free, since we give it up every
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* switch (ie, no lazy save of the vector registers).
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* On entry: r13 == 'current' && last_task_used_altivec != 'current'
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*/
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_STATIC(load_up_altivec)
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mfmsr r5 /* grab the current MSR */
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oris r5,r5,MSR_VEC@h
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mtmsrd r5 /* enable use of VMX now */
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isync
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/*
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* For SMP, we don't do lazy VMX switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_altvec in switch_to.
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* VRSAVE isn't dealt with here, that is done in the normal context
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* switch code. Note that we could rely on vrsave value to eventually
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* avoid saving all of the VREGs here...
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*/
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#ifndef CONFIG_SMP
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ld r3,last_task_used_altivec@got(r2)
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ld r4,0(r3)
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cmpdi 0,r4,0
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beq 1f
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/* Save VMX state to last_task_used_altivec's THREAD struct */
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addi r4,r4,THREAD
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SAVE_32VRS(0,r5,r4)
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mfvscr vr0
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li r10,THREAD_VSCR
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stvx vr0,r10,r4
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/* Disable VMX for last_task_used_altivec */
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ld r5,PT_REGS(r4)
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ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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lis r6,MSR_VEC@h
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andc r4,r4,r6
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std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* Hack: if we get an altivec unavailable trap with VRSAVE
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* set to all zeros, we assume this is a broken application
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* that fails to set it properly, and thus we switch it to
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* all 1's
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*/
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mfspr r4,SPRN_VRSAVE
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cmpdi 0,r4,0
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bne+ 1f
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li r4,-1
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mtspr SPRN_VRSAVE,r4
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1:
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/* enable use of VMX after return */
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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oris r12,r12,MSR_VEC@h
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std r12,_MSR(r1)
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li r4,1
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li r10,THREAD_VSCR
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stw r4,THREAD_USED_VR(r5)
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lvx vr0,r10,r5
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mtvscr vr0
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REST_32VRS(0,r4,r5)
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#ifndef CONFIG_SMP
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/* Update last_task_used_math to 'current' */
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subi r4,r5,THREAD /* Back to 'current' */
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std r4,0(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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b fast_exception_return
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#endif /* CONFIG_ALTIVEC */
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/*
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* Hash table stuff
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*/
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@ -1152,6 +1256,27 @@ unrecov_slb:
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bl .unrecoverable_exception
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b 1b
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/*
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* Data area reserved for FWNMI option.
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* This address (0x7000) is fixed by the RPA.
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*/
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.= 0x7000
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.globl fwnmi_data_area
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fwnmi_data_area:
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.space PAGE_SIZE
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/*
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* Space for the initial segment table
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* For LPAR, the hypervisor must fill in at least one entry
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* before we get control (with relocate on)
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*/
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. = STAB0_PHYS_ADDR
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.globl __start_stab
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__start_stab:
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. = (STAB0_PHYS_ADDR + PAGE_SIZE)
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.globl __end_stab
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__end_stab:
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/*
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* On pSeries, secondary processors spin in the following code.
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@ -1415,62 +1540,6 @@ _GLOBAL(copy_and_flush)
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.align 8
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copy_to_here:
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/*
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* load_up_fpu(unused, unused, tsk)
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* Disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Enables the FPU for use in the kernel on return.
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* On SMP we know the fpu is free, since we give it up every
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* switch (ie, no lazy save of the FP registers).
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* On entry: r13 == 'current' && last_task_used_math != 'current'
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*/
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_STATIC(load_up_fpu)
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mfmsr r5 /* grab the current MSR */
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ori r5,r5,MSR_FP
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mtmsrd r5 /* enable use of fpu now */
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isync
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/*
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* For SMP, we don't do lazy FPU switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_fpu in switch_to.
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*
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*/
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#ifndef CONFIG_SMP
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ld r3,last_task_used_math@got(r2)
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ld r4,0(r3)
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cmpdi 0,r4,0
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beq 1f
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/* Save FP state to last_task_used_math's THREAD struct */
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addi r4,r4,THREAD
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SAVE_32FPRS(0, r4)
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mffs fr0
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stfd fr0,THREAD_FPSCR(r4)
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/* Disable FP for last_task_used_math */
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ld r5,PT_REGS(r4)
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ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r6,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r6
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std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* enable use of FP after return */
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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ld r4,THREAD_FPEXC_MODE(r5)
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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lfd fr0,THREAD_FPSCR(r5)
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mtfsf 0xff,fr0
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REST_32FPRS(0, r5)
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#ifndef CONFIG_SMP
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/* Update last_task_used_math to 'current' */
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subi r4,r5,THREAD /* Back to 'current' */
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std r4,0(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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b fast_exception_return
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/*
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* disable_kernel_fp()
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* Disable the FPU.
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@ -1515,81 +1584,7 @@ _GLOBAL(giveup_fpu)
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#endif /* CONFIG_SMP */
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blr
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#ifdef CONFIG_ALTIVEC
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/*
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* load_up_altivec(unused, unused, tsk)
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* Disable VMX for the task which had it previously,
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* and save its vector registers in its thread_struct.
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* Enables the VMX for use in the kernel on return.
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* On SMP we know the VMX is free, since we give it up every
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* switch (ie, no lazy save of the vector registers).
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* On entry: r13 == 'current' && last_task_used_altivec != 'current'
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*/
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_STATIC(load_up_altivec)
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mfmsr r5 /* grab the current MSR */
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oris r5,r5,MSR_VEC@h
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mtmsrd r5 /* enable use of VMX now */
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isync
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/*
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* For SMP, we don't do lazy VMX switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_altvec in switch_to.
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* VRSAVE isn't dealt with here, that is done in the normal context
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* switch code. Note that we could rely on vrsave value to eventually
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* avoid saving all of the VREGs here...
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*/
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#ifndef CONFIG_SMP
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ld r3,last_task_used_altivec@got(r2)
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ld r4,0(r3)
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cmpdi 0,r4,0
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beq 1f
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/* Save VMX state to last_task_used_altivec's THREAD struct */
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addi r4,r4,THREAD
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SAVE_32VRS(0,r5,r4)
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mfvscr vr0
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li r10,THREAD_VSCR
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stvx vr0,r10,r4
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/* Disable VMX for last_task_used_altivec */
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ld r5,PT_REGS(r4)
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ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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lis r6,MSR_VEC@h
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andc r4,r4,r6
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std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* Hack: if we get an altivec unavailable trap with VRSAVE
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* set to all zeros, we assume this is a broken application
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* that fails to set it properly, and thus we switch it to
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* all 1's
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*/
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mfspr r4,SPRN_VRSAVE
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cmpdi 0,r4,0
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bne+ 1f
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li r4,-1
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mtspr SPRN_VRSAVE,r4
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1:
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/* enable use of VMX after return */
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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oris r12,r12,MSR_VEC@h
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std r12,_MSR(r1)
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li r4,1
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li r10,THREAD_VSCR
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stw r4,THREAD_USED_VR(r5)
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lvx vr0,r10,r5
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mtvscr vr0
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REST_32VRS(0,r4,r5)
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#ifndef CONFIG_SMP
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/* Update last_task_used_math to 'current' */
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subi r4,r5,THREAD /* Back to 'current' */
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std r4,0(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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b fast_exception_return
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/*
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* disable_kernel_altivec()
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* Disable the VMX.
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