forked from luck/tmp_suning_uos_patched
net: atlantic: HW bindings for basic A2 init/deinit hw_ops
This patch adds A2 register definitions for basic A2 HW initialization / deinitialization. Signed-off-by: Dmitry Bogdanov <dbogdanov@marvell.com> Co-developed-by: Egor Pomozov <epomozov@marvell.com> Signed-off-by: Egor Pomozov <epomozov@marvell.com> Co-developed-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Co-developed-by: Nikita Danilov <ndanilov@marvell.com> Signed-off-by: Nikita Danilov <ndanilov@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry Bogdanov
David S. Miller
parent
3417368494
commit
ec7629e0c2
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@ -58,6 +58,55 @@ void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)
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tag);
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}
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/* TX */
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void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR,
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HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK,
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HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT,
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clk_gate_en);
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}
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void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
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u32 max_credit,
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u32 tc)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
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HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK,
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HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT,
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max_credit);
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}
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void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
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u32 tx_pkt_shed_tc_data_weight,
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u32 tc)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc),
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HW_ATL2_TPS_DATA_TCTWEIGHT_MSK,
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HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT,
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tx_pkt_shed_tc_data_weight);
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}
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u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR);
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}
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void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw)
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{
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u32 hw_ver = hw_atl2_get_hw_version(aq_hw);
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aq_hw_write_reg_bit(aq_hw, HW_ATL2_LT_CTRL_ADR,
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HW_ATL2_LT_CTRL_CLK_RATIO_MSK,
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HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT,
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hw_ver < HW_ATL2_FPGA_VER_U32(1, 0, 0, 0) ?
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HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED :
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hw_ver >= HW_ATL2_FPGA_VER_U32(1, 0, 85, 2) ?
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HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED :
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HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED);
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}
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/* set action resolver record */
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void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,
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u32 tag, u32 mask, u32 action)
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@ -128,3 +177,24 @@ u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw)
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HW_ATL2_MIF_MCP_FINISHED_READ_MSK,
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HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT);
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}
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u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR);
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}
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void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val)
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{
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return aq_hw_write_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR, val);
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}
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u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_ADR);
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}
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void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val)
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{
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return aq_hw_write_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR,
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val);
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}
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@ -29,6 +29,23 @@ void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,
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/* Set VLAN filter tag */
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void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter);
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/* set tx buffer clock gate enable */
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void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en);
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/* set tx packet scheduler tc data max credit */
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void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
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u32 max_credit,
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u32 tc);
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/* set tx packet scheduler tc data weight */
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void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
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u32 tx_pkt_shed_tc_data_weight,
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u32 tc);
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u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw);
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void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw);
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/* set action resolver record */
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void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,
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u32 tag, u32 mask, u32 action);
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@ -54,4 +71,16 @@ void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish);
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/* get mcp finished read shared buffer indication */
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u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw);
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/* get mcp boot register */
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u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw);
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/* set mcp boot register */
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void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val);
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/* get host interrupt request */
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u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw);
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/* clear host interrupt request */
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void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val);
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#endif /* HW_ATL2_LLH_H */
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@ -105,6 +105,105 @@
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/* default value of bitfield vlan_req_tag0{f}[3:0] */
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#define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0
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/* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]".
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* Parameter: Queue {Q} | bit-level stride | range [0, 31]
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* PORT="pif_rx_q0_tc_map_i[2:0]"
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*/
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/* Register address for bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_ADR(queue) \
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(((queue) < 32) ? 0x00005900 + ((queue) / 8) * 4 : 0)
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/* Lower bit position of bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_SHIFT(queue) \
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(((queue) < 32) ? ((queue) * 4) % 32 : 0)
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/* Width of bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_WIDTH 3
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/* Default value of bitfield rx_q{Q}_tc_map[2:0] */
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#define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0
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/* tx tx_buffer_clk_gate_en bitfield definitions
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* preprocessor definitions for the bitfield "tx_buffer_clk_gate_en".
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* port="pif_tpb_tx_buffer_clk_gate_en_i"
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*/
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/* register address for bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR 0x00007900
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/* bitmask for bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK 0x00000020
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/* inverted bitmask for bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSKN 0xffffffdf
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/* lower bit position of bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT 5
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/* width of bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_WIDTH 1
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/* default value of bitfield tx_buffer_clk_gate_en */
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#define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT 0x0
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/* tx data_tc{t}_credit_max[b:0] bitfield definitions
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* preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
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* parameter: tc {t} | stride size 0x4 | range [0, 7]
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* port="pif_tps_data_tc0_credit_max_i[11:0]"
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*/
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/* register address for bitfield data_tc{t}_credit_max[b:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
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/* bitmask for bitfield data_tc{t}_credit_max[b:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000
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/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff
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/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
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/* width of bitfield data_tc{t}_credit_max[b:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 12
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/* default value of bitfield data_tc{t}_credit_max[b:0] */
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#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
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/* tx data_tc{t}_weight[8:0] bitfield definitions
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* preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
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* parameter: tc {t} | stride size 0x4 | range [0, 7]
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* port="pif_tps_data_tc0_weight_i[8:0]"
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*/
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/* register address for bitfield data_tc{t}_weight[8:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
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/* bitmask for bitfield data_tc{t}_weight[8:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x000001ff
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/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00
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/* lower bit position of bitfield data_tc{t}_weight[8:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT 0
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/* width of bitfield data_tc{t}_weight[8:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 9
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/* default value of bitfield data_tc{t}_weight[8:0] */
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#define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
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/* Launch time control register */
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#define HW_ATL2_LT_CTRL_ADR 0x00007a1c
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#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_MSK 0xFFFF0000
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#define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_SHIFT 16
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#define HW_ATL2_LT_CTRL_CLK_RATIO_MSK 0x0000FF00
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#define HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT 8
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#define HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED 4
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#define HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED 2
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#define HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED 1
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#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_MSK 0x00000008
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#define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_SHIFT 3
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#define HW_ATL2_LT_CTRL_LINK_SPEED_MSK 0x00000007
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#define HW_ATL2_LT_CTRL_LINK_SPEED_SHIFT 0
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/* FPGA VER register */
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#define HW_ATL2_FPGA_VER_ADR 0x000000f4
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#define HW_ATL2_FPGA_VER_U32(mj, mi, bl, rv) \
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((((mj) & 0xff) << 24) | \
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(((mi) & 0xff) << 16) | \
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(((bl) & 0xff) << 8) | \
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(((rv) & 0xff) << 0))
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/* ahb_mem_addr{f}[31:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]".
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* Parameter: filter {f} | stride size 0x10 | range [0, 127]
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@ -209,4 +308,13 @@
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/* Default value of bitfield pif_mcp_finished_buf_rd_i */
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#define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0
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/* Register address for bitfield pif_mcp_boot_reg */
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#define HW_ATL2_MIF_BOOT_REG_ADR 0x00003040u
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#define HW_ATL2_MCP_HOST_REQ_INT_READY BIT(0)
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#define HW_ATL2_MCP_HOST_REQ_INT_ADR 0x00000F00u
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#define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR 0x00000F04u
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#define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR 0x00000F08u
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#endif /* HW_ATL2_LLH_INTERNAL_H */
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