AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

dt-bindings: add binding for the Allwinner DE2 CCU

Browse Source 
Allwinner "Display Engine 2.0" contains some clock controls in it.

In order to add them as clock drivers, we need a device tree binding.
Add the binding here.

Also add the device tree binding headers.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Icenowy Zheng 2017-05-15 00:30:33 +08:00 committed by Maxime Ripard
parent d85da227c3
commit ed74f8a8a6
3 changed files with 63 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
Documentation/devicetree/bindings/clock/sun8i-de2.txt Normal file
View File

@ -0,0 +1,31 @@
Allwinner Display Engine 2.0 Clock Control Binding
--------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- "mod": the display engine module clock
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
de2_clocks: clock@1000000 {
compatible = "allwinner,sun8i-a83t-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};

18
include/dt-bindings/clock/sun8i-de2.h Normal file
View File

@ -0,0 +1,18 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
#define CLK_BUS_MIXER0 0
#define CLK_BUS_MIXER1 1
#define CLK_BUS_WB 2
#define CLK_MIXER0 6
#define CLK_MIXER1 7
#define CLK_WB 8
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */

14
include/dt-bindings/reset/sun8i-de2.h Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
#define RST_MIXER0 0
#define RST_MIXER1 1
#define RST_WB 2
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */