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dw_dmac: Allow src/dst msize & flow controller to be configured at runtime

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Msize or Burst Size is peripheral dependent in case of prep_slave_sg and
cyclic_prep transfers, and in case of memcpy transfers it is platform dependent.
So msize configuration must come from platform data.

Also some peripherals (ex: JPEG), need to be flow controller for dma transfers,
so this information in case of slave_sg & cyclic_prep transfers must come from
platform data.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Viresh KUMAR 2011-03-04 15:42:51 +05:30 committed by Vinod Koul
parent 59c22fc11d
commit ee66509d7f
3 changed files with 39 additions and 6 deletions
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14
drivers/dma/dw_dmac.c
View File

@ -36,9 +36,11 @@
struct dw_dma_slave *__slave = (private); \ struct dw_dma_slave *__slave = (private); \
int dms = __slave ? __slave->dst_master : 0; \ int dms = __slave ? __slave->dst_master : 0; \
int sms = __slave ? __slave->src_master : 1; \ int sms = __slave ? __slave->src_master : 1; \
u8 smsize = __slave ? __slave->src_msize : 0; \
u8 dmsize = __slave ? __slave->dst_msize : 0; \
\ \
(DWC_CTLL_DST_MSIZE(0) \ (DWC_CTLL_DST_MSIZE(dmsize) \
| DWC_CTLL_SRC_MSIZE(0) \ | DWC_CTLL_SRC_MSIZE(smsize) \
| DWC_CTLL_LLP_D_EN \ | DWC_CTLL_LLP_D_EN \
| DWC_CTLL_LLP_S_EN \ | DWC_CTLL_LLP_S_EN \
| DWC_CTLL_DMS(dms) \ | DWC_CTLL_DMS(dms) \
@ -683,7 +685,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
| DWC_CTLL_DST_WIDTH(reg_width) | DWC_CTLL_DST_WIDTH(reg_width)
| DWC_CTLL_DST_FIX | DWC_CTLL_DST_FIX
| DWC_CTLL_SRC_INC | DWC_CTLL_SRC_INC
| DWC_CTLL_FC_M2P); | DWC_CTLL_FC(dws->fc));
reg = dws->tx_reg; reg = dws->tx_reg;
for_each_sg(sgl, sg, sg_len, i) { for_each_sg(sgl, sg, sg_len, i) {
struct dw_desc *desc; struct dw_desc *desc;
@ -728,7 +730,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
| DWC_CTLL_SRC_WIDTH(reg_width) | DWC_CTLL_SRC_WIDTH(reg_width)
| DWC_CTLL_DST_INC | DWC_CTLL_DST_INC
| DWC_CTLL_SRC_FIX | DWC_CTLL_SRC_FIX
| DWC_CTLL_FC_P2M); | DWC_CTLL_FC(dws->fc));
reg = dws->rx_reg; reg = dws->rx_reg;
for_each_sg(sgl, sg, sg_len, i) { for_each_sg(sgl, sg, sg_len, i) {
@ -1146,7 +1148,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
| DWC_CTLL_SRC_WIDTH(reg_width) | DWC_CTLL_SRC_WIDTH(reg_width)
| DWC_CTLL_DST_FIX | DWC_CTLL_DST_FIX
| DWC_CTLL_SRC_INC | DWC_CTLL_SRC_INC
| DWC_CTLL_FC_M2P | DWC_CTLL_FC(dws->fc)
| DWC_CTLL_INT_EN); | DWC_CTLL_INT_EN);
break; break;
case DMA_FROM_DEVICE: case DMA_FROM_DEVICE:
@ -1157,7 +1159,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
| DWC_CTLL_DST_WIDTH(reg_width) | DWC_CTLL_DST_WIDTH(reg_width)
| DWC_CTLL_DST_INC | DWC_CTLL_DST_INC
| DWC_CTLL_SRC_FIX | DWC_CTLL_SRC_FIX
| DWC_CTLL_FC_P2M | DWC_CTLL_FC(dws->fc)
| DWC_CTLL_INT_EN); | DWC_CTLL_INT_EN);
break; break;
default: default:

1
drivers/dma/dw_dmac_regs.h
View File

@ -86,6 +86,7 @@ struct dw_dma_regs {
#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ #define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ #define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
#define DWC_CTLL_FC(n) ((n) << 20)
#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ #define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ #define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ #define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */

30
include/linux/dw_dmac.h
View File

@ -42,6 +42,30 @@ enum dw_dma_slave_width {
DW_DMA_SLAVE_WIDTH_32BIT, DW_DMA_SLAVE_WIDTH_32BIT,
}; };
/* bursts size */
enum dw_dma_msize {
DW_DMA_MSIZE_1,
DW_DMA_MSIZE_4,
DW_DMA_MSIZE_8,
DW_DMA_MSIZE_16,
DW_DMA_MSIZE_32,
DW_DMA_MSIZE_64,
DW_DMA_MSIZE_128,
DW_DMA_MSIZE_256,
};
/* flow controller */
enum dw_dma_fc {
DW_DMA_FC_D_M2M,
DW_DMA_FC_D_M2P,
DW_DMA_FC_D_P2M,
DW_DMA_FC_D_P2P,
DW_DMA_FC_P_P2M,
DW_DMA_FC_SP_P2P,
DW_DMA_FC_P_M2P,
DW_DMA_FC_DP_P2P,
};
/** /**
* struct dw_dma_slave - Controller-specific information about a slave * struct dw_dma_slave - Controller-specific information about a slave
* *
@ -55,6 +79,9 @@ enum dw_dma_slave_width {
* @cfg_lo: Platform-specific initializer for the CFG_LO register * @cfg_lo: Platform-specific initializer for the CFG_LO register
* @src_master: src master for transfers on allocated channel. * @src_master: src master for transfers on allocated channel.
* @dst_master: dest master for transfers on allocated channel. * @dst_master: dest master for transfers on allocated channel.
* @src_msize: src burst size.
* @dst_msize: dest burst size.
* @fc: flow controller for DMA transfer
*/ */
struct dw_dma_slave { struct dw_dma_slave {
struct device *dma_dev; struct device *dma_dev;
@ -65,6 +92,9 @@ struct dw_dma_slave {
u32 cfg_lo; u32 cfg_lo;
u8 src_master; u8 src_master;
u8 dst_master; u8 dst_master;
u8 src_msize;
u8 dst_msize;
u8 fc;
}; };
/* Platform-configurable bits in CFG_HI */ /* Platform-configurable bits in CFG_HI */