forked from luck/tmp_suning_uos_patched
KVM: arm64: GICv4.1: Add direct injection capability to SGI registers
Most of the GICv3 emulation code that deals with SGIs now has to be aware of the v4.1 capabilities in order to benefit from it. Add such support, keyed on the interrupt having the hw flag set and being a SGI. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Link: https://lore.kernel.org/r/20200304203330.4967-19-maz@kernel.org
This commit is contained in:
Marc Zyngier
parent
9879b79aef
commit
ef1820be47
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@ -6,6 +6,7 @@
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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@ -257,8 +258,18 @@ static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
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*/
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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bool state = irq->pending_latch;
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if (irq->pending_latch)
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if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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int err;
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err = irq_get_irqchip_state(irq->host_irq,
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IRQCHIP_STATE_PENDING,
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&state);
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WARN_ON(err);
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}
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if (state)
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value |= (1U << i);
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vgic_put_irq(vcpu->kvm, irq);
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@ -942,8 +953,18 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
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* generate interrupts of either group.
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*/
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if (!irq->group || allow_group1) {
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if (!irq->hw) {
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irq->pending_latch = true;
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vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
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} else {
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/* HW SGI? Ask the GIC to inject it */
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int err;
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err = irq_set_irqchip_state(irq->host_irq,
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IRQCHIP_STATE_PENDING,
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true);
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WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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}
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} else {
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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}
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@ -5,6 +5,8 @@
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#include <linux/bitops.h>
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#include <linux/bsearch.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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@ -59,6 +61,11 @@ unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
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return value;
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}
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static void vgic_update_vsgi(struct vgic_irq *irq)
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{
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WARN_ON(its_prop_update_vsgi(irq->host_irq, irq->priority, irq->group));
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}
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void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val)
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{
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@ -71,7 +78,12 @@ void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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irq->group = !!(val & BIT(i));
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if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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vgic_update_vsgi(irq);
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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} else {
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vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
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}
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vgic_put_irq(vcpu->kvm, irq);
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}
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@ -113,7 +125,21 @@ void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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if (vgic_irq_is_mapped_level(irq)) {
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if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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if (!irq->enabled) {
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struct irq_data *data;
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irq->enabled = true;
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data = &irq_to_desc(irq->host_irq)->irq_data;
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while (irqd_irq_disabled(data))
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enable_irq(irq->host_irq);
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}
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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continue;
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} else if (vgic_irq_is_mapped_level(irq)) {
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bool was_high = irq->line_level;
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/*
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@ -148,6 +174,8 @@ void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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if (irq->hw && vgic_irq_is_sgi(irq->intid) && irq->enabled)
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disable_irq_nosync(irq->host_irq);
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irq->enabled = false;
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@ -167,10 +195,22 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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unsigned long flags;
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bool val;
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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if (irq_is_pending(irq))
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value |= (1U << i);
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if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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int err;
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val = false;
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err = irq_get_irqchip_state(irq->host_irq,
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IRQCHIP_STATE_PENDING,
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&val);
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WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
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} else {
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val = irq_is_pending(irq);
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}
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value |= ((u32)val << i);
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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@ -215,6 +255,21 @@ void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
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}
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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/* HW SGI? Ask the GIC to inject it */
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int err;
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err = irq_set_irqchip_state(irq->host_irq,
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IRQCHIP_STATE_PENDING,
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true);
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WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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continue;
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}
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if (irq->hw)
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vgic_hw_irq_spending(vcpu, irq, is_uaccess);
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else
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@ -269,6 +324,20 @@ void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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/* HW SGI? Ask the GIC to clear its pending bit */
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int err;
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err = irq_set_irqchip_state(irq->host_irq,
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IRQCHIP_STATE_PENDING,
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false);
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WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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continue;
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}
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if (irq->hw)
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vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
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else
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@ -318,8 +387,15 @@ static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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if (irq->hw) {
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if (irq->hw && !vgic_irq_is_sgi(irq->intid)) {
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vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
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} else if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
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/*
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* GICv4.1 VSGI feature doesn't track an active state,
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* so let's not kid ourselves, there is nothing we can
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* do here.
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*/
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irq->active = false;
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} else {
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u32 model = vcpu->kvm->arch.vgic.vgic_model;
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u8 active_source;
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@ -493,6 +569,8 @@ void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
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raw_spin_lock_irqsave(&irq->irq_lock, flags);
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/* Narrow the priority range to what we actually support */
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irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
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if (irq->hw && vgic_irq_is_sgi(irq->intid))
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vgic_update_vsgi(irq);
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raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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