forked from luck/tmp_suning_uos_patched
Second and final device tree updates towards 5.10-rc1 for TI K3 platform.
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This commit is contained in:
Olof Johansson
commit
ef3c139ba0
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@ -1,26 +0,0 @@
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Texas Instruments K3 Multicore SoC architecture device tree bindings
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||||||
--------------------------------------------------------------------
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||||||
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Platforms based on Texas Instruments K3 Multicore SoC architecture
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shall follow the following scheme:
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SoCs
|
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||||||
----
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Each device tree root node must specify which exact SoC in K3 Multicore SoC
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||||||
architecture it uses, using one of the following compatible values:
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- AM654
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compatible = "ti,am654";
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- J721E
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compatible = "ti,j721e";
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Boards
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||||||
------
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In addition, each device tree root node must specify which one or more
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of the following board-specific compatible values:
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- AM654 EVM
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compatible = "ti,am654-evm", "ti,am654";
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35
Documentation/devicetree/bindings/arm/ti/k3.yaml
Normal file
35
Documentation/devicetree/bindings/arm/ti/k3.yaml
Normal file
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@ -0,0 +1,35 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments K3 Multicore SoC architecture device tree bindings
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maintainers:
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- Nishanth Menon <nm@ti.com>
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description: |
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Platforms based on Texas Instruments K3 Multicore SoC architecture
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shall have the following properties.
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: K3 AM654 SoC
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items:
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- enum:
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- ti,am654-evm
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- const: ti,am654
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- description: K3 J721E SoC
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items:
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- const: ti,j721e
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- description: K3 J7200 SoC
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items:
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- const: ti,j7200
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...
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@ -2637,7 +2637,7 @@ M: Tero Kristo <t-kristo@ti.com>
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M: Nishanth Menon <nm@ti.com>
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M: Nishanth Menon <nm@ti.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Supported
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S: Supported
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F: Documentation/devicetree/bindings/arm/ti/k3.txt
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F: Documentation/devicetree/bindings/arm/ti/k3.yaml
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F: arch/arm64/boot/dts/ti/Makefile
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F: arch/arm64/boot/dts/ti/Makefile
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F: arch/arm64/boot/dts/ti/k3-*
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F: arch/arm64/boot/dts/ti/k3-*
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F: include/dt-bindings/pinctrl/k3.h
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F: include/dt-bindings/pinctrl/k3.h
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@ -3,9 +3,11 @@
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# Make file to build device tree binaries for boards based on
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# Make file to build device tree binaries for boards based on
|
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# Texas Instruments Inc processors
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# Texas Instruments Inc processors
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#
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#
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# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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#
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#
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dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
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dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
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215
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
Normal file
215
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
Normal file
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@ -0,0 +1,215 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j7200-som-p0.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/mux/ti-serdes.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
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};
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};
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&wkup_pmx0 {
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mcu_cpsw_pins_default: mcu-cpsw-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
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J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
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J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
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J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
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J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
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J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
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J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
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J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
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J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
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J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
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J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
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J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu-mdio1-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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};
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&main_pmx0 {
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
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J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
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>;
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};
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
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J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
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J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
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J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
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J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
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J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
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J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
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J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
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J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
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>;
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};
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main_usbss0_pins_default: main-usbss0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
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>;
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};
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};
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "disabled";
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};
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&main_uart0 {
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/* Shared with ATF on this platform */
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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|
&main_uart2 {
|
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|
/* MAIN UART 2 is used by R5F firmware */
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status = "disabled";
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|
};
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|
&main_uart3 {
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|
/* UART not brought out */
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status = "disabled";
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};
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|
&main_uart4 {
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|
/* UART not brought out */
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status = "disabled";
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};
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|
&main_uart5 {
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|
/* UART not brought out */
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|
status = "disabled";
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};
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|
&main_uart6 {
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|
/* UART not brought out */
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|
status = "disabled";
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|
};
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|
|
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|
&main_uart7 {
|
||||||
|
/* UART not brought out */
|
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|
status = "disabled";
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|
};
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|
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|
&main_uart8 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
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|
};
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|
&main_uart9 {
|
||||||
|
/* UART not brought out */
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|
status = "disabled";
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||||||
|
};
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|
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|
&mcu_cpsw {
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|
pinctrl-names = "default";
|
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|
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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|
};
|
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|
|
||||||
|
&davinci_mdio {
|
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|
phy0: ethernet-phy@0 {
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|
reg = <0>;
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|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
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|
};
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|
};
|
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|
|
||||||
|
&cpsw_port1 {
|
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|
phy-mode = "rgmii-rxid";
|
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|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_i2c0 {
|
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|
pinctrl-names = "default";
|
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|
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
|
||||||
|
exp1: gpio@20 {
|
||||||
|
compatible = "ti,tca6416";
|
||||||
|
reg = <0x20>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
exp2: gpio@22 {
|
||||||
|
compatible = "ti,tca6424";
|
||||||
|
reg = <0x22>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_i2c1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
|
||||||
|
exp4: gpio@20 {
|
||||||
|
compatible = "ti,tca6408";
|
||||||
|
reg = <0x20>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci0 {
|
||||||
|
/* eMMC */
|
||||||
|
non-removable;
|
||||||
|
ti,driver-strength-ohm = <50>;
|
||||||
|
disable-wp;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci1 {
|
||||||
|
/* SD card */
|
||||||
|
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
ti,driver-strength-ohm = <50>;
|
||||||
|
disable-wp;
|
||||||
|
};
|
||||||
|
|
||||||
|
&serdes_ln_ctrl {
|
||||||
|
idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
|
||||||
|
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_serdes_mux {
|
||||||
|
idle-states = <1>; /* USB0 to SERDES lane 3 */
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbss0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||||
|
ti,vbus-divider;
|
||||||
|
ti,usb2-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb0 {
|
||||||
|
dr_mode = "otg";
|
||||||
|
maximum-speed = "high-speed";
|
||||||
|
};
|
||||||
449
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
Normal file
449
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
Normal file
|
|
@ -0,0 +1,449 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Device Tree Source for J7200 SoC Family Main Domain peripherals
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
&cbass_main {
|
||||||
|
msmc_ram: sram@70000000 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <0x00 0x70000000 0x00 0x100000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x00 0x00 0x70000000 0x100000>;
|
||||||
|
|
||||||
|
atf-sram@0 {
|
||||||
|
reg = <0x00 0x20000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
scm_conf: scm-conf@100000 {
|
||||||
|
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||||
|
reg = <0x00 0x00100000 0x00 0x1c000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x00 0x00 0x00100000 0x1c000>;
|
||||||
|
|
||||||
|
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
|
||||||
|
compatible = "mmio-mux";
|
||||||
|
#mux-control-cells = <1>;
|
||||||
|
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
|
||||||
|
<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
|
||||||
|
};
|
||||||
|
|
||||||
|
usb_serdes_mux: mux-controller@4000 {
|
||||||
|
compatible = "mmio-mux";
|
||||||
|
#mux-control-cells = <1>;
|
||||||
|
mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gic500: interrupt-controller@1800000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||||
|
<0x00 0x01900000 0x00 0x100000>; /* GICR */
|
||||||
|
|
||||||
|
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||||
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
gic_its: msi-controller@1820000 {
|
||||||
|
compatible = "arm,gic-v3-its";
|
||||||
|
reg = <0x00 0x01820000 0x00 0x10000>;
|
||||||
|
socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
||||||
|
msi-controller;
|
||||||
|
#msi-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
main_gpio_intr: interrupt-controller0 {
|
||||||
|
compatible = "ti,sci-intr";
|
||||||
|
ti,intr-trigger-type = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
interrupt-parent = <&gic500>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <131>;
|
||||||
|
ti,interrupt-ranges = <8 392 56>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_navss: bus@30000000 {
|
||||||
|
compatible = "simple-mfd";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
|
||||||
|
ti,sci-dev-id = <199>;
|
||||||
|
|
||||||
|
main_navss_intr: interrupt-controller1 {
|
||||||
|
compatible = "ti,sci-intr";
|
||||||
|
ti,intr-trigger-type = <4>;
|
||||||
|
interrupt-controller;
|
||||||
|
interrupt-parent = <&gic500>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <213>;
|
||||||
|
ti,interrupt-ranges = <0 64 64>,
|
||||||
|
<64 448 64>,
|
||||||
|
<128 672 64>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_udmass_inta: msi-controller@33d00000 {
|
||||||
|
compatible = "ti,sci-inta";
|
||||||
|
reg = <0x00 0x33d00000 0x00 0x100000>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <0>;
|
||||||
|
interrupt-parent = <&main_navss_intr>;
|
||||||
|
msi-controller;
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <209>;
|
||||||
|
ti,interrupt-ranges = <0 0 256>;
|
||||||
|
};
|
||||||
|
|
||||||
|
secure_proxy_main: mailbox@32c00000 {
|
||||||
|
compatible = "ti,am654-secure-proxy";
|
||||||
|
#mbox-cells = <1>;
|
||||||
|
reg-names = "target_data", "rt", "scfg";
|
||||||
|
reg = <0x00 0x32c00000 0x00 0x100000>,
|
||||||
|
<0x00 0x32400000 0x00 0x100000>,
|
||||||
|
<0x00 0x32800000 0x00 0x100000>;
|
||||||
|
interrupt-names = "rx_011";
|
||||||
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_ringacc: ringacc@3c000000 {
|
||||||
|
compatible = "ti,am654-navss-ringacc";
|
||||||
|
reg = <0x00 0x3c000000 0x00 0x400000>,
|
||||||
|
<0x00 0x38000000 0x00 0x400000>,
|
||||||
|
<0x00 0x31120000 0x00 0x100>,
|
||||||
|
<0x00 0x33000000 0x00 0x40000>;
|
||||||
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||||
|
ti,num-rings = <1024>;
|
||||||
|
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <211>;
|
||||||
|
msi-parent = <&main_udmass_inta>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_udmap: dma-controller@31150000 {
|
||||||
|
compatible = "ti,j721e-navss-main-udmap";
|
||||||
|
reg = <0x00 0x31150000 0x00 0x100>,
|
||||||
|
<0x00 0x34000000 0x00 0x100000>,
|
||||||
|
<0x00 0x35000000 0x00 0x100000>;
|
||||||
|
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||||
|
msi-parent = <&main_udmass_inta>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <212>;
|
||||||
|
ti,ringacc = <&main_ringacc>;
|
||||||
|
|
||||||
|
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||||
|
<0x0f>, /* TX_HCHAN */
|
||||||
|
<0x10>; /* TX_UHCHAN */
|
||||||
|
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||||
|
<0x0b>, /* RX_HCHAN */
|
||||||
|
<0x0c>; /* RX_UHCHAN */
|
||||||
|
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||||
|
};
|
||||||
|
|
||||||
|
cpts@310d0000 {
|
||||||
|
compatible = "ti,j721e-cpts";
|
||||||
|
reg = <0x00 0x310d0000 0x00 0x400>;
|
||||||
|
reg-names = "cpts";
|
||||||
|
clocks = <&k3_clks 201 1>;
|
||||||
|
clock-names = "cpts";
|
||||||
|
interrupts-extended = <&main_navss_intr 391>;
|
||||||
|
interrupt-names = "cpts";
|
||||||
|
ti,cpts-periodic-outputs = <6>;
|
||||||
|
ti,cpts-ext-ts-inputs = <8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
main_pmx0: pinctrl@11c000 {
|
||||||
|
compatible = "pinctrl-single";
|
||||||
|
/* Proxy 0 addressing */
|
||||||
|
reg = <0x00 0x11c000 0x00 0x2b4>;
|
||||||
|
#pinctrl-cells = <1>;
|
||||||
|
pinctrl-single,register-width = <32>;
|
||||||
|
pinctrl-single,function-mask = <0xffffffff>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart0: serial@2800000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02800000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 146 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart1: serial@2810000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02810000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 278 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart2: serial@2820000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02820000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 279 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart3: serial@2830000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02830000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 280 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart4: serial@2840000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02840000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 281 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart5: serial@2850000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02850000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 282 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart6: serial@2860000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02860000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 283 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart7: serial@2870000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02870000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 284 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart8: serial@2880000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02880000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 285 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart9: serial@2890000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02890000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 286 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c0: i2c@2000000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2000000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 187 1>;
|
||||||
|
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c1: i2c@2010000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2010000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 188 1>;
|
||||||
|
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c2: i2c@2020000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2020000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 189 1>;
|
||||||
|
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c3: i2c@2030000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2030000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 190 1>;
|
||||||
|
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c4: i2c@2040000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2040000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 191 1>;
|
||||||
|
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c5: i2c@2050000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2050000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 192 1>;
|
||||||
|
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c6: i2c@2060000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x2060000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 193 1>;
|
||||||
|
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_sdhci0: mmc@4f80000 {
|
||||||
|
compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
|
||||||
|
reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
|
||||||
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clock-names = "clk_xin", "clk_ahb";
|
||||||
|
clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
|
||||||
|
ti,otap-del-sel-legacy = <0x0>;
|
||||||
|
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||||
|
ti,otap-del-sel-ddr52 = <0x6>;
|
||||||
|
ti,otap-del-sel-hs200 = <0x8>;
|
||||||
|
ti,otap-del-sel-hs400 = <0x0>;
|
||||||
|
ti,strobe-sel = <0x77>;
|
||||||
|
ti,trm-icp = <0x8>;
|
||||||
|
bus-width = <8>;
|
||||||
|
mmc-ddr-1_8v;
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_sdhci1: mmc@4fb0000 {
|
||||||
|
compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
|
||||||
|
reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
|
||||||
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clock-names = "clk_xin", "clk_ahb";
|
||||||
|
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
|
||||||
|
ti,otap-del-sel-legacy = <0x0>;
|
||||||
|
ti,otap-del-sel-sd-hs = <0x0>;
|
||||||
|
ti,otap-del-sel-sdr12 = <0xf>;
|
||||||
|
ti,otap-del-sel-sdr25 = <0xf>;
|
||||||
|
ti,otap-del-sel-sdr50 = <0xc>;
|
||||||
|
ti,otap-del-sel-sdr104 = <0x5>;
|
||||||
|
ti,otap-del-sel-ddr50 = <0xc>;
|
||||||
|
no-1-8-v;
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
usbss0: cdns-usb@4104000 {
|
||||||
|
compatible = "ti,j721e-usb";
|
||||||
|
reg = <0x00 0x4104000 0x00 0x100>;
|
||||||
|
dma-coherent;
|
||||||
|
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
|
||||||
|
clock-names = "ref", "lpm";
|
||||||
|
assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
|
||||||
|
assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
usb0: usb@6000000 {
|
||||||
|
compatible = "cdns,usb3";
|
||||||
|
reg = <0x00 0x6000000 0x00 0x10000>,
|
||||||
|
<0x00 0x6010000 0x00 0x10000>,
|
||||||
|
<0x00 0x6020000 0x00 0x10000>;
|
||||||
|
reg-names = "otg", "xhci", "dev";
|
||||||
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||||
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||||
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
||||||
|
interrupt-names = "host",
|
||||||
|
"peripheral",
|
||||||
|
"otg";
|
||||||
|
maximum-speed = "super-speed";
|
||||||
|
dr_mode = "otg";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
273
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
Normal file
273
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
Normal file
|
|
@ -0,0 +1,273 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
&cbass_mcu_wakeup {
|
||||||
|
dmsc: dmsc@44083000 {
|
||||||
|
compatible = "ti,k2g-sci";
|
||||||
|
ti,host-id = <12>;
|
||||||
|
|
||||||
|
mbox-names = "rx", "tx";
|
||||||
|
|
||||||
|
mboxes= <&secure_proxy_main 11>,
|
||||||
|
<&secure_proxy_main 13>;
|
||||||
|
|
||||||
|
reg-names = "debug_messages";
|
||||||
|
reg = <0x00 0x44083000 0x00 0x1000>;
|
||||||
|
|
||||||
|
k3_pds: power-controller {
|
||||||
|
compatible = "ti,sci-pm-domain";
|
||||||
|
#power-domain-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
k3_clks: clocks {
|
||||||
|
compatible = "ti,k2g-sci-clk";
|
||||||
|
#clock-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
k3_reset: reset-controller {
|
||||||
|
compatible = "ti,sci-reset";
|
||||||
|
#reset-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_conf: syscon@40f00000 {
|
||||||
|
compatible = "syscon", "simple-mfd";
|
||||||
|
reg = <0x00 0x40f00000 0x00 0x20000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x00 0x00 0x40f00000 0x20000>;
|
||||||
|
|
||||||
|
phy_gmii_sel: phy@4040 {
|
||||||
|
compatible = "ti,am654-phy-gmii-sel";
|
||||||
|
reg = <0x4040 0x4>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
chipid@43000014 {
|
||||||
|
compatible = "ti,am654-chipid";
|
||||||
|
reg = <0x00 0x43000014 0x00 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_pmx0: pinctrl@4301c000 {
|
||||||
|
compatible = "pinctrl-single";
|
||||||
|
/* Proxy 0 addressing */
|
||||||
|
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||||
|
#pinctrl-cells = <1>;
|
||||||
|
pinctrl-single,register-width = <32>;
|
||||||
|
pinctrl-single,function-mask = <0xffffffff>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_ram: sram@41c00000 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <0x00 0x41c00000 0x00 0x100000>;
|
||||||
|
ranges = <0x00 0x00 0x41c00000 0x100000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_uart0: serial@42300000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x42300000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 287 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_uart0: serial@40a00000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <96000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 149 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_gpio_intr: interrupt-controller2 {
|
||||||
|
compatible = "ti,sci-intr";
|
||||||
|
ti,intr-trigger-type = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
interrupt-parent = <&gic500>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <137>;
|
||||||
|
ti,interrupt-ranges = <16 960 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_navss: bus@28380000 {
|
||||||
|
compatible = "simple-mfd";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||||
|
dma-coherent;
|
||||||
|
dma-ranges;
|
||||||
|
ti,sci-dev-id = <232>;
|
||||||
|
|
||||||
|
mcu_ringacc: ringacc@2b800000 {
|
||||||
|
compatible = "ti,am654-navss-ringacc";
|
||||||
|
reg = <0x00 0x2b800000 0x00 0x400000>,
|
||||||
|
<0x00 0x2b000000 0x00 0x400000>,
|
||||||
|
<0x00 0x28590000 0x00 0x100>,
|
||||||
|
<0x00 0x2a500000 0x00 0x40000>;
|
||||||
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||||
|
ti,num-rings = <286>;
|
||||||
|
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <235>;
|
||||||
|
msi-parent = <&main_udmass_inta>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_udmap: dma-controller@285c0000 {
|
||||||
|
compatible = "ti,j721e-navss-mcu-udmap";
|
||||||
|
reg = <0x00 0x285c0000 0x00 0x100>,
|
||||||
|
<0x00 0x2a800000 0x00 0x40000>,
|
||||||
|
<0x00 0x2aa00000 0x00 0x40000>;
|
||||||
|
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||||
|
msi-parent = <&main_udmass_inta>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <236>;
|
||||||
|
ti,ringacc = <&mcu_ringacc>;
|
||||||
|
|
||||||
|
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||||
|
<0x0f>; /* TX_HCHAN */
|
||||||
|
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||||
|
<0x0b>; /* RX_HCHAN */
|
||||||
|
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_cpsw: ethernet@46000000 {
|
||||||
|
compatible = "ti,j721e-cpsw-nuss";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
reg = <0x00 0x46000000 0x00 0x200000>;
|
||||||
|
reg-names = "cpsw_nuss";
|
||||||
|
ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
|
||||||
|
dma-coherent;
|
||||||
|
clocks = <&k3_clks 18 21>;
|
||||||
|
clock-names = "fck";
|
||||||
|
power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
|
||||||
|
dmas = <&mcu_udmap 0xf000>,
|
||||||
|
<&mcu_udmap 0xf001>,
|
||||||
|
<&mcu_udmap 0xf002>,
|
||||||
|
<&mcu_udmap 0xf003>,
|
||||||
|
<&mcu_udmap 0xf004>,
|
||||||
|
<&mcu_udmap 0xf005>,
|
||||||
|
<&mcu_udmap 0xf006>,
|
||||||
|
<&mcu_udmap 0xf007>,
|
||||||
|
<&mcu_udmap 0x7000>;
|
||||||
|
dma-names = "tx0", "tx1", "tx2", "tx3",
|
||||||
|
"tx4", "tx5", "tx6", "tx7",
|
||||||
|
"rx";
|
||||||
|
|
||||||
|
ethernet-ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpsw_port1: port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
ti,mac-only;
|
||||||
|
label = "port1";
|
||||||
|
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||||
|
phys = <&phy_gmii_sel 1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
davinci_mdio: mdio@f00 {
|
||||||
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||||
|
reg = <0x00 0xf00 0x00 0x100>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clocks = <&k3_clks 18 21>;
|
||||||
|
clock-names = "fck";
|
||||||
|
bus_freq = <1000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpts@3d000 {
|
||||||
|
compatible = "ti,am65-cpts";
|
||||||
|
reg = <0x00 0x3d000 0x00 0x400>;
|
||||||
|
clocks = <&k3_clks 18 2>;
|
||||||
|
clock-names = "cpts";
|
||||||
|
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "cpts";
|
||||||
|
ti,cpts-ext-ts-inputs = <4>;
|
||||||
|
ti,cpts-periodic-outputs = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_i2c0: i2c@40b00000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x40b00000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 194 1>;
|
||||||
|
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_i2c1: i2c@40b10000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x40b10000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 195 1>;
|
||||||
|
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_i2c0: i2c@42120000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x00 0x42120000 0x00 0x100>;
|
||||||
|
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 197 1>;
|
||||||
|
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
|
||||||
|
};
|
||||||
|
|
||||||
|
fss: syscon@47000000 {
|
||||||
|
compatible = "syscon", "simple-mfd";
|
||||||
|
reg = <0x00 0x47000000 0x00 0x100>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
hbmc_mux: hbmc-mux {
|
||||||
|
compatible = "mmio-mux";
|
||||||
|
#mux-control-cells = <1>;
|
||||||
|
mux-reg-masks = <0x4 0x2>; /* HBMC select */
|
||||||
|
};
|
||||||
|
|
||||||
|
hbmc: hyperbus@47034000 {
|
||||||
|
compatible = "ti,am654-hbmc";
|
||||||
|
reg = <0x00 0x47034000 0x00 0x100>,
|
||||||
|
<0x05 0x00000000 0x01 0x0000000>;
|
||||||
|
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 102 0>;
|
||||||
|
assigned-clocks = <&k3_clks 102 5>;
|
||||||
|
assigned-clock-rates = <333333333>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
mux-controls = <&hbmc_mux 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
65
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
Normal file
65
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
Normal file
|
|
@ -0,0 +1,65 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "k3-j7200.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
memory@80000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
/* 4G RAM */
|
||||||
|
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||||
|
<0x08 0x80000000 0x00 0x80000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reserved_memory: reserved-memory {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
secure_ddr: optee@9e800000 {
|
||||||
|
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||||
|
alignment = <0x1000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_pmx0 {
|
||||||
|
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
|
||||||
|
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
|
||||||
|
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
|
||||||
|
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
|
||||||
|
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
|
||||||
|
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
|
||||||
|
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
|
||||||
|
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
|
||||||
|
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
|
||||||
|
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
|
||||||
|
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
||||||
|
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
||||||
|
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&hbmc {
|
||||||
|
/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
|
||||||
|
* appropriate node based on board detection
|
||||||
|
*/
|
||||||
|
status = "disabled";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
||||||
|
ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
|
||||||
|
<0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
|
||||||
|
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "cypress,hyperflash", "cfi-flash";
|
||||||
|
reg = <0x00 0x00 0x4000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
172
arch/arm64/boot/dts/ti/k3-j7200.dtsi
Normal file
172
arch/arm64/boot/dts/ti/k3-j7200.dtsi
Normal file
|
|
@ -0,0 +1,172 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Device Tree Source for J7200 SoC Family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/pinctrl/k3.h>
|
||||||
|
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Texas Instruments K3 J7200 SoC";
|
||||||
|
compatible = "ti,j7200";
|
||||||
|
interrupt-parent = <&gic500>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &wkup_uart0;
|
||||||
|
serial1 = &mcu_uart0;
|
||||||
|
serial2 = &main_uart0;
|
||||||
|
serial3 = &main_uart1;
|
||||||
|
serial4 = &main_uart2;
|
||||||
|
serial5 = &main_uart3;
|
||||||
|
serial6 = &main_uart4;
|
||||||
|
serial7 = &main_uart5;
|
||||||
|
serial8 = &main_uart6;
|
||||||
|
serial9 = &main_uart7;
|
||||||
|
serial10 = &main_uart8;
|
||||||
|
serial11 = &main_uart9;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen { };
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cpu-map {
|
||||||
|
cluster0: cluster0 {
|
||||||
|
core0 {
|
||||||
|
cpu = <&cpu0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
core1 {
|
||||||
|
cpu = <&cpu1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu0: cpu@0 {
|
||||||
|
compatible = "arm,cortex-a72";
|
||||||
|
reg = <0x000>;
|
||||||
|
device_type = "cpu";
|
||||||
|
enable-method = "psci";
|
||||||
|
i-cache-size = <0xc000>;
|
||||||
|
i-cache-line-size = <64>;
|
||||||
|
i-cache-sets = <256>;
|
||||||
|
d-cache-size = <0x8000>;
|
||||||
|
d-cache-line-size = <64>;
|
||||||
|
d-cache-sets = <128>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu1: cpu@1 {
|
||||||
|
compatible = "arm,cortex-a72";
|
||||||
|
reg = <0x001>;
|
||||||
|
device_type = "cpu";
|
||||||
|
enable-method = "psci";
|
||||||
|
i-cache-size = <0xc000>;
|
||||||
|
i-cache-line-size = <64>;
|
||||||
|
i-cache-sets = <256>;
|
||||||
|
d-cache-size = <0x8000>;
|
||||||
|
d-cache-line-size = <64>;
|
||||||
|
d-cache-sets = <128>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
L2_0: l2-cache0 {
|
||||||
|
compatible = "cache";
|
||||||
|
cache-level = <2>;
|
||||||
|
cache-size = <0x100000>;
|
||||||
|
cache-line-size = <64>;
|
||||||
|
cache-sets = <2048>;
|
||||||
|
next-level-cache = <&msmc_l3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
msmc_l3: l3-cache0 {
|
||||||
|
compatible = "cache";
|
||||||
|
cache-level = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
firmware {
|
||||||
|
optee {
|
||||||
|
compatible = "linaro,optee-tz";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
|
||||||
|
psci: psci {
|
||||||
|
compatible = "arm,psci-1.0";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
a72_timer0: timer-cl0-cpu0 {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||||
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||||
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||||
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||||
|
};
|
||||||
|
|
||||||
|
pmu: pmu {
|
||||||
|
compatible = "arm,armv8-pmuv3";
|
||||||
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cbass_main: bus@100000 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||||
|
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||||
|
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
|
||||||
|
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||||
|
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||||
|
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
|
||||||
|
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||||
|
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||||
|
|
||||||
|
/* MCUSS_WKUP Range */
|
||||||
|
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||||
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||||
|
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||||
|
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||||
|
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||||
|
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||||
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||||
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||||
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||||
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||||
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||||
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||||
|
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||||
|
|
||||||
|
cbass_mcu_wakeup: bus@28380000 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||||
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||||
|
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||||
|
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||||
|
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||||
|
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||||
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||||
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||||
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||||
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||||
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||||
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
|
||||||
|
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Now include the peripherals for each bus segments */
|
||||||
|
#include "k3-j7200-main.dtsi"
|
||||||
|
#include "k3-j7200-mcu-wakeup.dtsi"
|
||||||
|
|
@ -311,11 +311,12 @@ &usb_serdes_mux {
|
||||||
};
|
};
|
||||||
|
|
||||||
&serdes_ln_ctrl {
|
&serdes_ln_ctrl {
|
||||||
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
|
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
|
||||||
<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
|
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
|
||||||
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
|
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
|
||||||
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
|
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
|
||||||
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
|
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
|
||||||
|
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
|
||||||
};
|
};
|
||||||
|
|
||||||
&serdes_wiz3 {
|
&serdes_wiz3 {
|
||||||
|
|
@ -407,7 +408,7 @@ exp2: gpio@22 {
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
|
|
||||||
p09 {
|
p09-hog {
|
||||||
/* P11 - MCASP/TRACE_MUX_S0 */
|
/* P11 - MCASP/TRACE_MUX_S0 */
|
||||||
gpio-hog;
|
gpio-hog;
|
||||||
gpios = <9 GPIO_ACTIVE_HIGH>;
|
gpios = <9 GPIO_ACTIVE_HIGH>;
|
||||||
|
|
@ -415,7 +416,7 @@ p09 {
|
||||||
line-name = "MCASP/TRACE_MUX_S0";
|
line-name = "MCASP/TRACE_MUX_S0";
|
||||||
};
|
};
|
||||||
|
|
||||||
p10 {
|
p10-hog {
|
||||||
/* P12 - MCASP/TRACE_MUX_S1 */
|
/* P12 - MCASP/TRACE_MUX_S1 */
|
||||||
gpio-hog;
|
gpio-hog;
|
||||||
gpios = <10 GPIO_ACTIVE_HIGH>;
|
gpios = <10 GPIO_ACTIVE_HIGH>;
|
||||||
|
|
|
||||||
|
|
@ -6,7 +6,7 @@
|
||||||
*/
|
*/
|
||||||
#include <dt-bindings/phy/phy.h>
|
#include <dt-bindings/phy/phy.h>
|
||||||
#include <dt-bindings/mux/mux.h>
|
#include <dt-bindings/mux/mux.h>
|
||||||
#include <dt-bindings/mux/mux-j721e-wiz.h>
|
#include <dt-bindings/mux/ti-serdes.h>
|
||||||
|
|
||||||
&cbass_main {
|
&cbass_main {
|
||||||
msmc_ram: sram@70000000 {
|
msmc_ram: sram@70000000 {
|
||||||
|
|
@ -70,11 +70,12 @@ serdes_ln_ctrl: mux@4080 {
|
||||||
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
|
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
|
||||||
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
|
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
|
||||||
/* SERDES4 lane0/1/2/3 select */
|
/* SERDES4 lane0/1/2/3 select */
|
||||||
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
|
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
|
||||||
<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
|
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
|
||||||
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
|
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
|
||||||
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
|
<MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
|
||||||
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
|
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
|
||||||
|
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
|
||||||
};
|
};
|
||||||
|
|
||||||
usb_serdes_mux: mux-controller@4000 {
|
usb_serdes_mux: mux-controller@4000 {
|
||||||
|
|
|
||||||
|
|
@ -1,53 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
|
||||||
/*
|
|
||||||
* This header provides constants for J721E WIZ.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _DT_BINDINGS_J721E_WIZ
|
|
||||||
#define _DT_BINDINGS_J721E_WIZ
|
|
||||||
|
|
||||||
#define SERDES0_LANE0_QSGMII_LANE1 0x0
|
|
||||||
#define SERDES0_LANE0_PCIE0_LANE0 0x1
|
|
||||||
#define SERDES0_LANE0_USB3_0_SWAP 0x2
|
|
||||||
|
|
||||||
#define SERDES0_LANE1_QSGMII_LANE2 0x0
|
|
||||||
#define SERDES0_LANE1_PCIE0_LANE1 0x1
|
|
||||||
#define SERDES0_LANE1_USB3_0 0x2
|
|
||||||
|
|
||||||
#define SERDES1_LANE0_QSGMII_LANE3 0x0
|
|
||||||
#define SERDES1_LANE0_PCIE1_LANE0 0x1
|
|
||||||
#define SERDES1_LANE0_USB3_1_SWAP 0x2
|
|
||||||
#define SERDES1_LANE0_SGMII_LANE0 0x3
|
|
||||||
|
|
||||||
#define SERDES1_LANE1_QSGMII_LANE4 0x0
|
|
||||||
#define SERDES1_LANE1_PCIE1_LANE1 0x1
|
|
||||||
#define SERDES1_LANE1_USB3_1 0x2
|
|
||||||
#define SERDES1_LANE1_SGMII_LANE1 0x3
|
|
||||||
|
|
||||||
#define SERDES2_LANE0_PCIE2_LANE0 0x1
|
|
||||||
#define SERDES2_LANE0_SGMII_LANE0 0x3
|
|
||||||
#define SERDES2_LANE0_USB3_1_SWAP 0x2
|
|
||||||
|
|
||||||
#define SERDES2_LANE1_PCIE2_LANE1 0x1
|
|
||||||
#define SERDES2_LANE1_USB3_1 0x2
|
|
||||||
#define SERDES2_LANE1_SGMII_LANE1 0x3
|
|
||||||
|
|
||||||
#define SERDES3_LANE0_PCIE3_LANE0 0x1
|
|
||||||
#define SERDES3_LANE0_USB3_0_SWAP 0x2
|
|
||||||
|
|
||||||
#define SERDES3_LANE1_PCIE3_LANE1 0x1
|
|
||||||
#define SERDES3_LANE1_USB3_0 0x2
|
|
||||||
|
|
||||||
#define SERDES4_LANE0_EDP_LANE0 0x0
|
|
||||||
#define SERDES4_LANE0_QSGMII_LANE5 0x2
|
|
||||||
|
|
||||||
#define SERDES4_LANE1_EDP_LANE1 0x0
|
|
||||||
#define SERDES4_LANE1_QSGMII_LANE6 0x2
|
|
||||||
|
|
||||||
#define SERDES4_LANE2_EDP_LANE2 0x0
|
|
||||||
#define SERDES4_LANE2_QSGMII_LANE7 0x2
|
|
||||||
|
|
||||||
#define SERDES4_LANE3_EDP_LANE3 0x0
|
|
||||||
#define SERDES4_LANE3_QSGMII_LANE8 0x2
|
|
||||||
|
|
||||||
#endif /* _DT_BINDINGS_J721E_WIZ */
|
|
||||||
93
include/dt-bindings/mux/ti-serdes.h
Normal file
93
include/dt-bindings/mux/ti-serdes.h
Normal file
|
|
@ -0,0 +1,93 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* This header provides constants for SERDES MUX for TI SoCs
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _DT_BINDINGS_MUX_TI_SERDES
|
||||||
|
#define _DT_BINDINGS_MUX_TI_SERDES
|
||||||
|
|
||||||
|
/* J721E */
|
||||||
|
|
||||||
|
#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
|
||||||
|
#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
|
||||||
|
#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
|
||||||
|
#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
|
||||||
|
#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
|
||||||
|
#define J721E_SERDES0_LANE1_USB3_0 0x2
|
||||||
|
#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
|
||||||
|
#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
|
||||||
|
#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
|
||||||
|
#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
|
||||||
|
#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
|
||||||
|
#define J721E_SERDES1_LANE1_USB3_1 0x2
|
||||||
|
#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
|
||||||
|
#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
|
||||||
|
#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
|
||||||
|
#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
|
||||||
|
#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
|
||||||
|
#define J721E_SERDES2_LANE1_USB3_1 0x2
|
||||||
|
#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
|
||||||
|
#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
|
||||||
|
#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
|
||||||
|
#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
|
||||||
|
#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
|
||||||
|
#define J721E_SERDES3_LANE1_USB3_0 0x2
|
||||||
|
#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
|
||||||
|
#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
|
||||||
|
#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
|
||||||
|
#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
|
||||||
|
#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
|
||||||
|
#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
|
||||||
|
#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
|
||||||
|
#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
|
||||||
|
#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
|
||||||
|
#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
|
||||||
|
#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
|
||||||
|
#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
|
||||||
|
#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
/* J7200 */
|
||||||
|
|
||||||
|
#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
|
||||||
|
#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
|
||||||
|
#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
|
||||||
|
#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
|
||||||
|
#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
|
||||||
|
#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
|
||||||
|
#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
|
||||||
|
#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
|
||||||
|
#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
|
||||||
|
#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
|
||||||
|
#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
|
||||||
|
#define J7200_SERDES0_LANE3_USB 0x2
|
||||||
|
#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
|
||||||
|
|
||||||
|
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
|
||||||
Loading…
Reference in New Issue
Block a user