forked from luck/tmp_suning_uos_patched
irqchip: Add Loongson PCH PIC controller
This controller appears on Loongson LS7A family of PCH to transform interrupts from devices into HyperTransport vectorized interrrupts and send them to procrssor's HT vector controller. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200528152757.1028711-4-jiaxun.yang@flygoat.com
This commit is contained in:
Jiaxun Yang
Marc Zyngier
parent
6c2832c3c6
commit
ef8c01eb64
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@ -540,4 +540,13 @@ config LOONGSON_HTVEC
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help
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Support for the Loongson3 HyperTransport Interrupt Vector Controller.
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config LOONGSON_PCH_PIC
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bool "Loongson PCH PIC Controller"
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depends on MACH_LOONGSON64 || COMPILE_TEST
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default MACH_LOONGSON64
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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help
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Support for the Loongson PCH PIC Controller.
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endmenu
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@ -108,3 +108,4 @@ obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
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obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
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obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
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obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
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obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
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243
drivers/irqchip/irq-loongson-pch-pic.c
Normal file
243
drivers/irqchip/irq-loongson-pch-pic.c
Normal file
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@ -0,0 +1,243 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
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* Loongson PCH PIC support
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*/
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#define pr_fmt(fmt) "pch-pic: " fmt
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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/* Registers */
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#define PCH_PIC_MASK 0x20
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#define PCH_PIC_HTMSI_EN 0x40
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#define PCH_PIC_EDGE 0x60
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#define PCH_PIC_CLR 0x80
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#define PCH_PIC_AUTO0 0xc0
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#define PCH_PIC_AUTO1 0xe0
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#define PCH_INT_ROUTE(irq) (0x100 + irq)
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#define PCH_INT_HTVEC(irq) (0x200 + irq)
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#define PCH_PIC_POL 0x3e0
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#define PIC_COUNT_PER_REG 32
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#define PIC_REG_COUNT 2
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#define PIC_COUNT (PIC_COUNT_PER_REG * PIC_REG_COUNT)
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#define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG)
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#define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG)
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struct pch_pic {
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void __iomem *base;
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struct irq_domain *pic_domain;
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u32 ht_vec_base;
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raw_spinlock_t pic_lock;
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};
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static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
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{
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u32 reg;
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void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4;
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raw_spin_lock(&priv->pic_lock);
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reg = readl(addr);
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reg |= BIT(PIC_REG_BIT(bit));
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writel(reg, addr);
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raw_spin_unlock(&priv->pic_lock);
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}
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static void pch_pic_bitclr(struct pch_pic *priv, int offset, int bit)
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{
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u32 reg;
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void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4;
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raw_spin_lock(&priv->pic_lock);
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reg = readl(addr);
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reg &= ~BIT(PIC_REG_BIT(bit));
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writel(reg, addr);
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raw_spin_unlock(&priv->pic_lock);
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}
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static void pch_pic_eoi_irq(struct irq_data *d)
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{
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u32 idx = PIC_REG_IDX(d->hwirq);
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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writel(BIT(PIC_REG_BIT(d->hwirq)),
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priv->base + PCH_PIC_CLR + idx * 4);
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}
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static void pch_pic_mask_irq(struct irq_data *d)
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{
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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pch_pic_bitset(priv, PCH_PIC_MASK, d->hwirq);
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irq_chip_mask_parent(d);
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}
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static void pch_pic_unmask_irq(struct irq_data *d)
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{
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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irq_chip_unmask_parent(d);
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pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq);
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}
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static int pch_pic_set_type(struct irq_data *d, unsigned int type)
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{
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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int ret = 0;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);
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pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);
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pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);
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pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);
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pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static struct irq_chip pch_pic_irq_chip = {
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.name = "PCH PIC",
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.irq_mask = pch_pic_mask_irq,
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.irq_unmask = pch_pic_unmask_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_eoi = pch_pic_eoi_irq,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = pch_pic_set_type,
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};
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static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int err;
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unsigned int type;
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unsigned long hwirq;
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struct irq_fwspec fwspec;
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struct pch_pic *priv = domain->host_data;
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irq_domain_translate_twocell(domain, arg, &hwirq, &type);
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 1;
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fwspec.param[0] = hwirq + priv->ht_vec_base;
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (err)
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return err;
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irq_domain_set_info(domain, virq, hwirq,
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&pch_pic_irq_chip, priv,
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handle_fasteoi_ack_irq, NULL, NULL);
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irq_set_probe(virq);
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return 0;
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}
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static const struct irq_domain_ops pch_pic_domain_ops = {
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.translate = irq_domain_translate_twocell,
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.alloc = pch_pic_alloc,
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.free = irq_domain_free_irqs_parent,
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};
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static void pch_pic_reset(struct pch_pic *priv)
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{
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int i;
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for (i = 0; i < PIC_COUNT; i++) {
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/* Write vectore ID */
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writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
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/* Hardcode route to HT0 Lo */
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writeb(1, priv->base + PCH_INT_ROUTE(i));
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}
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for (i = 0; i < PIC_REG_COUNT; i++) {
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/* Clear IRQ cause registers, mask all interrupts */
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writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_MASK + 4 * i);
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writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_CLR + 4 * i);
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/* Clear auto bounce, we don't need that */
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writel_relaxed(0, priv->base + PCH_PIC_AUTO0 + 4 * i);
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writel_relaxed(0, priv->base + PCH_PIC_AUTO1 + 4 * i);
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/* Enable HTMSI transformer */
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writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_HTMSI_EN + 4 * i);
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}
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}
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static int pch_pic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct pch_pic *priv;
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struct irq_domain *parent_domain;
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int err;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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raw_spin_lock_init(&priv->pic_lock);
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priv->base = of_iomap(node, 0);
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if (!priv->base) {
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err = -ENOMEM;
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goto free_priv;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("Failed to find the parent domain\n");
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err = -ENXIO;
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goto iounmap_base;
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}
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if (of_property_read_u32(node, "loongson,pic-base-vec",
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&priv->ht_vec_base)) {
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pr_err("Failed to determine pic-base-vec\n");
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err = -EINVAL;
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goto iounmap_base;
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}
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priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
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PIC_COUNT,
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of_node_to_fwnode(node),
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&pch_pic_domain_ops,
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priv);
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if (!priv->pic_domain) {
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pr_err("Failed to create IRQ domain\n");
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err = -ENOMEM;
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goto iounmap_base;
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}
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pch_pic_reset(priv);
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return 0;
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iounmap_base:
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iounmap(priv->base);
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free_priv:
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kfree(priv);
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return err;
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}
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IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);
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