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[POWERPC] DTS cleanup

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Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came from
* Removed big-endian from i8259 pic nodes, this was just bogus

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2007-09-12 11:52:31 -05:00
parent 5d54ddcbcf
commit f0c8ac8083
25 changed files with 4 additions and 99 deletions
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1
arch/powerpc/boot/dts/holly.dts
View File

@ -31,7 +31,6 @@ PowerPC,750CL@0 {
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
32-bit;
};
};

2
arch/powerpc/boot/dts/kuroboxHD.dts
View File

@ -47,7 +47,6 @@ memory {
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@ -101,7 +100,6 @@ mpic: interrupt-controller@80040000 {
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
built-in;
};
pci@fec00000 {

2
arch/powerpc/boot/dts/kuroboxHG.dts
View File

@ -47,7 +47,6 @@ memory {
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@ -101,7 +100,6 @@ mpic: interrupt-controller@80040000 {
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
built-in;
};
pci@fec00000 {

7
arch/powerpc/boot/dts/lite5200.dts
View File

@ -37,7 +37,6 @@ PowerPC,5200@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -50,10 +49,9 @@ soc5200@f0000000 {
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
reg = <f0000000 00010000>;
ranges = <0 f0000000 0000c000>;
reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
@ -69,7 +67,6 @@ mpc5200_pic: pic@500 {
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
built-in;
};
gpt@600 { // General Purpose Timer

7
arch/powerpc/boot/dts/lite5200b.dts
View File

@ -37,7 +37,6 @@ PowerPC,5200@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -50,10 +49,9 @@ soc5200@f0000000 {
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
reg = <f0000000 00010000>;
ranges = <0 f0000000 0000c000>;
reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
@ -69,7 +67,6 @@ mpc5200_pic: pic@500 {
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
reg = <500 80>;
built-in;
};
gpt@600 { // General Purpose Timer

4
arch/powerpc/boot/dts/mpc7448hpc2.dts
View File

@ -31,7 +31,6 @@ PowerPC,7448@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
32-bit;
};
};
@ -44,7 +43,6 @@ memory {
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
@ -128,7 +126,6 @@ mpic: pic@7400 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -180,7 +177,6 @@ RT0: router@1180 {
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;

5
arch/powerpc/boot/dts/mpc8272ads.dts
View File

@ -29,7 +29,6 @@ PowerPC,8272@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -38,7 +37,6 @@ pci_pic: interrupt-controller@f8200000 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <f8200000 f8200004>;
built-in;
device_type = "pci-pic";
};
@ -56,7 +54,6 @@ chosen {
soc8272@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 f0000000 00053000>;
reg = <f0000000 10000>;
@ -118,7 +115,6 @@ ethernet@25000 {
cpm@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
@ -161,7 +157,6 @@ cpm_pic:interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
built-in;
device_type = "cpm-pic";
compatible = "CPM2";
};

3
arch/powerpc/boot/dts/mpc8313erdb.dts
View File

@ -29,7 +29,6 @@ PowerPC,8313@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -41,7 +40,6 @@ memory {
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -207,7 +205,6 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};

4
arch/powerpc/boot/dts/mpc832x_mds.dts
View File

@ -29,7 +29,6 @@ PowerPC,8323@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -46,7 +45,6 @@ bcsr@f8000000 {
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -163,7 +161,6 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
@ -333,7 +330,6 @@ qeic: qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;

4
arch/powerpc/boot/dts/mpc832x_rdb.dts
View File

@ -29,7 +29,6 @@ PowerPC,8323@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -41,7 +40,6 @@ memory {
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -132,7 +130,6 @@ pic:pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
@ -292,7 +289,6 @@ qeic:qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;

3
arch/powerpc/boot/dts/mpc8349emitx.dts
View File

@ -28,7 +28,6 @@ PowerPC,8349@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -40,7 +39,6 @@ memory {
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -244,7 +242,6 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};

3
arch/powerpc/boot/dts/mpc8349emitxgp.dts
View File

@ -28,7 +28,6 @@ PowerPC,8349@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -40,7 +39,6 @@ memory {
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -176,7 +174,6 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};

3
arch/powerpc/boot/dts/mpc834x_mds.dts
View File

@ -29,7 +29,6 @@ PowerPC,8349@0 {
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -46,7 +45,6 @@ bcsr@e2400000 {
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -332,7 +330,6 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};

4
arch/powerpc/boot/dts/mpc836x_mds.dts
View File

@ -34,7 +34,6 @@ PowerPC,8360@0 {
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
32-bit;
};
};
@ -51,7 +50,6 @@ bcsr@f8000000 {
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -178,7 +176,6 @@ ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
@ -364,7 +361,6 @@ qeic: qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;

3
arch/powerpc/boot/dts/mpc8540ads.dts
View File

@ -30,7 +30,6 @@ PowerPC,8540@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,7 +41,6 @@ memory {
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
@ -268,7 +266,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;

6
arch/powerpc/boot/dts/mpc8541cds.dts
View File

@ -30,7 +30,6 @@ PowerPC,8541@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,7 +41,6 @@ memory {
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
@ -197,15 +195,12 @@ pci1: pci@8000 {
device_type = "pci";
i8259@19000 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
interrupt-parent = <&pci1>;
};
@ -240,7 +235,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;

5
arch/powerpc/boot/dts/mpc8544ds.dts
View File

@ -30,7 +30,6 @@ PowerPC,8544@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -42,7 +41,6 @@ memory {
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
@ -295,12 +293,10 @@ i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
@ -350,7 +346,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;

5
arch/powerpc/boot/dts/mpc8548cds.dts
View File

@ -30,7 +30,6 @@ PowerPC,8548@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,7 +41,6 @@ memory {
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 e0001000 000ff000
80000000 80000000 10000000
@ -318,7 +316,6 @@ isa@4 {
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
@ -326,7 +323,6 @@ i8259: interrupt-controller@20 {
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
@ -394,7 +390,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;

6
arch/powerpc/boot/dts/mpc8555cds.dts
View File

@ -30,7 +30,6 @@ PowerPC,8555@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,7 +41,6 @@ memory {
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
@ -197,15 +195,12 @@ pci1: pci@8000 {
device_type = "pci";
i8259@19000 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
interrupt-parent = <&pci1>;
};
@ -240,7 +235,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;

5
arch/powerpc/boot/dts/mpc8560ads.dts
View File

@ -30,7 +30,6 @@ PowerPC,8560@0 {
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
32-bit;
};
};
@ -42,7 +41,6 @@ memory {
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -227,14 +225,12 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
device_type = "open-pic";
};
cpm@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <0 0 c0000>;
@ -249,7 +245,6 @@ cpmpic: pic@90c00 {
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
built-in;
device_type = "cpm-pic";
};

4
arch/powerpc/boot/dts/mpc8568mds.dts
View File

@ -34,7 +34,6 @@ PowerPC,8568@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -51,7 +50,6 @@ bcsr@f8000000 {
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>;
@ -258,7 +256,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -449,7 +446,6 @@ qeic: qeic@80 {
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupt-parent = <&mpic>;

6
arch/powerpc/boot/dts/mpc8641_hpcn.dts
View File

@ -30,7 +30,6 @@ PowerPC,8641@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
32-bit;
};
PowerPC,8641@1 {
device_type = "cpu";
@ -42,7 +41,6 @@ PowerPC,8641@1 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
32-bit;
};
};
@ -54,7 +52,6 @@ memory {
soc8641@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 f8001000 000ff000
80000000 80000000 20000000
@ -291,12 +288,10 @@ i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent =
@ -366,7 +361,6 @@ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;

5
arch/powerpc/boot/dts/mpc866ads.dts
View File

@ -30,7 +30,6 @@ PowerPC,866@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
@ -44,7 +43,6 @@ memory {
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
@ -78,7 +76,6 @@ mpc8xx_pic: pic@ff000000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
@ -86,7 +83,6 @@ mpc8xx_pic: pic@ff000000 {
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
@ -103,7 +99,6 @@ cpm_pic: pic@930 {
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
built-in;
device_type = "cpm-pic";
compatible = "CPM";
};

5
arch/powerpc/boot/dts/mpc885ads.dts
View File

@ -30,7 +30,6 @@ PowerPC,885@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
@ -44,7 +43,6 @@ memory {
soc885@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
@ -98,7 +96,6 @@ Mpc8xx_pic: pic@ff000000 {
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
@ -117,7 +114,6 @@ pcmcia@0080 {
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
@ -134,7 +130,6 @@ Cpm_pic: pic@930 {
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
built-in;
device_type = "cpm-pic";
compatible = "CPM";
};

1
arch/powerpc/boot/dts/prpmc2800.dts
View File

@ -43,7 +43,6 @@ memory {
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <1>;
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */