forked from luck/tmp_suning_uos_patched
bnxt_en: Update to firmware interface spec to 1.6.1.
Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
341138c3e6
commit
f183886c0d
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@ -1,7 +1,7 @@
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/* Broadcom NetXtreme-C/E network driver.
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*
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* Copyright (c) 2014-2016 Broadcom Corporation
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* Copyright (c) 2016 Broadcom Limited
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* Copyright (c) 2016-2017 Broadcom Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -11,12 +11,12 @@
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#ifndef BNXT_HSI_H
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#define BNXT_HSI_H
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/* HSI and HWRM Specification 1.6.0 */
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/* HSI and HWRM Specification 1.6.1 */
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#define HWRM_VERSION_MAJOR 1
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#define HWRM_VERSION_MINOR 6
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#define HWRM_VERSION_UPDATE 0
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#define HWRM_VERSION_UPDATE 1
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#define HWRM_VERSION_STR "1.6.0"
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#define HWRM_VERSION_STR "1.6.1"
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/*
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* Following is the signature for HWRM message field that indicates not
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* applicable (All F's). Need to cast it the size of the field if needed.
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@ -549,6 +549,8 @@ struct hwrm_ver_get_output {
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__le32 dev_caps_cfg;
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#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
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#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
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#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
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#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
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u8 roce_fw_maj;
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u8 roce_fw_min;
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u8 roce_fw_bld;
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@ -1919,6 +1921,219 @@ struct hwrm_port_phy_i2c_read_output {
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u8 valid;
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};
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/* hwrm_port_led_cfg */
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/* Input (64 bytes) */
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struct hwrm_port_led_cfg_input {
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__le16 req_type;
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__le16 cmpl_ring;
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__le16 seq_id;
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__le16 target_id;
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__le64 resp_addr;
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__le32 enables;
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#define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
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#define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
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#define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
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#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
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#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
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#define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
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#define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
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#define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
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#define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
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#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
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#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
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#define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
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#define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
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#define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
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__le16 port_id;
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u8 num_leds;
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u8 rsvd;
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u8 led0_id;
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u8 led0_state;
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#define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
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#define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
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#define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
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#define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
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u8 led0_color;
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#define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
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#define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
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#define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
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u8 unused_0;
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__le16 led0_blink_on;
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__le16 led0_blink_off;
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u8 led0_group_id;
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u8 rsvd0;
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u8 led1_id;
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u8 led1_state;
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#define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
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#define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
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#define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
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#define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
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u8 led1_color;
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#define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
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#define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
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#define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
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u8 unused_1;
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__le16 led1_blink_on;
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__le16 led1_blink_off;
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u8 led1_group_id;
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u8 rsvd1;
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u8 led2_id;
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u8 led2_state;
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#define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
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#define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
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#define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
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#define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
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u8 led2_color;
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#define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
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#define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
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#define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
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u8 unused_2;
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__le16 led2_blink_on;
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__le16 led2_blink_off;
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u8 led2_group_id;
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u8 rsvd2;
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u8 led3_id;
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u8 led3_state;
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#define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
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#define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
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#define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
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#define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
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u8 led3_color;
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#define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
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#define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
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#define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
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#define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
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u8 unused_3;
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__le16 led3_blink_on;
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__le16 led3_blink_off;
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u8 led3_group_id;
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u8 rsvd3;
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};
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/* Output (16 bytes) */
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struct hwrm_port_led_cfg_output {
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__le16 error_code;
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__le16 req_type;
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__le16 seq_id;
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__le16 resp_len;
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__le32 unused_0;
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u8 unused_1;
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u8 unused_2;
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u8 unused_3;
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u8 valid;
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};
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/* hwrm_port_led_qcaps */
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/* Input (24 bytes) */
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struct hwrm_port_led_qcaps_input {
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__le16 req_type;
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__le16 cmpl_ring;
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__le16 seq_id;
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__le16 target_id;
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__le64 resp_addr;
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__le16 port_id;
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__le16 unused_0[3];
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};
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/* Output (48 bytes) */
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struct hwrm_port_led_qcaps_output {
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__le16 error_code;
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__le16 req_type;
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__le16 seq_id;
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__le16 resp_len;
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u8 num_leds;
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u8 unused_0[3];
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u8 led0_id;
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u8 led0_type;
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#define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
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#define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
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#define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
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u8 led0_group_id;
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u8 unused_1;
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__le16 led0_state_caps;
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#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
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#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
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#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
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#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
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__le16 led0_color_caps;
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#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
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#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
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u8 led1_id;
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u8 led1_type;
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#define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
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#define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
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#define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
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u8 led1_group_id;
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u8 unused_2;
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__le16 led1_state_caps;
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#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
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#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
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#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
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#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
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__le16 led1_color_caps;
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#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
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#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
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u8 led2_id;
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u8 led2_type;
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#define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
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#define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
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#define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
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u8 led2_group_id;
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u8 unused_3;
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__le16 led2_state_caps;
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#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
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#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
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#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
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#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
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__le16 led2_color_caps;
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#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
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#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
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u8 led3_id;
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u8 led3_type;
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#define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
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#define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
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#define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
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u8 led3_group_id;
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u8 unused_4;
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__le16 led3_state_caps;
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#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
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#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
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#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
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#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
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__le16 led3_color_caps;
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#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
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#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
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#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
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u8 unused_5;
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u8 unused_6;
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u8 unused_7;
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u8 valid;
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};
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/* hwrm_queue_qportcfg */
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/* Input (24 bytes) */
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struct hwrm_queue_qportcfg_input {
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@ -4092,9 +4307,7 @@ struct hwrm_fw_set_structured_data_input {
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__le64 src_data_addr;
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__le16 data_len;
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u8 hdr_cnt;
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u8 unused_0;
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__le16 port_id;
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__le16 unused_1;
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u8 unused_0[5];
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};
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/* Output (16 bytes) */
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@ -4111,7 +4324,7 @@ struct hwrm_fw_set_structured_data_output {
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};
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/* hwrm_fw_get_structured_data */
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/* Input (40 bytes) */
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/* Input (32 bytes) */
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struct hwrm_fw_get_structured_data_input {
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__le16 req_type;
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__le16 cmpl_ring;
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@ -4131,8 +4344,6 @@ struct hwrm_fw_get_structured_data_input {
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#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
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u8 count;
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u8 unused_0;
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__le16 port_id;
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__le16 unused_1[3];
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};
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/* Output (16 bytes) */
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@ -4616,7 +4827,8 @@ struct hwrm_nvm_install_update_input {
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__le32 install_type;
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#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
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#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
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__le32 unused_0;
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__le16 flags;
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__le16 unused_0;
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};
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/* Output (24 bytes) */
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@ -4973,12 +5185,13 @@ struct ctx_hw_stats {
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struct hwrm_struct_hdr {
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__le16 struct_id;
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#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_ETS_CFG 0x41dUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_PFC_CFG 0x41fUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_APP_CFG 0x421UL
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#define STRUCT_HDR_STRUCT_ID_DCBX_STATE_CFG 0x422UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC_CFG 0x424UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE_CFG 0x426UL
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#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
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#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
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#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
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#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
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#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
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__le16 len;
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u8 version;
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u8 count;
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@ -4988,14 +5201,14 @@ struct hwrm_struct_hdr {
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__le16 unused_0[3];
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};
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/* DCBX Application configuration structure (8 bytes) */
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struct hwrm_struct_data_dcbx_app_cfg {
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__le16 protocol_id;
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/* DCBX Application configuration structure (1057) (8 bytes) */
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struct hwrm_struct_data_dcbx_app {
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__be16 protocol_id;
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u8 protocol_selector;
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#define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
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#define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
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#define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
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#define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
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#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
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#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
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#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
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#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
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u8 priority;
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u8 valid;
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u8 unused_0[3];
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