forked from luck/tmp_suning_uos_patched
i40e: Add NPAR BW get and set functions
We need to be able to get, set and commit permanently the NPAR partition BW configuration through configfs. These are necessary precursor functions for that feature. Also update the copyright year. Change-ID: I9d5ca160a9288145f1dd2042994028679fff55f3 Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Tested-by: Jim Young <james.m.young@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Greg Rose
Jeff Kirsher
parent
2bc7ee8ac5
commit
f4492db16d
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@ -385,6 +385,9 @@ struct i40e_pf {
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bool ptp_tx;
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bool ptp_rx;
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u16 rss_table_size;
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/* These are only valid in NPAR modes */
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u32 npar_max_bw;
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u32 npar_min_bw;
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};
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struct i40e_mac_filter {
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@ -732,4 +735,8 @@ int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
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int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
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void i40e_ptp_init(struct i40e_pf *pf);
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void i40e_ptp_stop(struct i40e_pf *pf);
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i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
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i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
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i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
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#endif /* _I40E_H_ */
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@ -3353,6 +3353,47 @@ i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
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return status;
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}
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/**
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* i40e_aq_alternate_read
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* @hw: pointer to the hardware structure
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* @reg_addr0: address of first dword to be read
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* @reg_val0: pointer for data read from 'reg_addr0'
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* @reg_addr1: address of second dword to be read
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* @reg_val1: pointer for data read from 'reg_addr1'
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*
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* Read one or two dwords from alternate structure. Fields are indicated
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* by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
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* is not passed then only register at 'reg_addr0' is read.
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*
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**/
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i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
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u32 reg_addr0, u32 *reg_val0,
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u32 reg_addr1, u32 *reg_val1)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_alternate_write *cmd_resp =
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(struct i40e_aqc_alternate_write *)&desc.params.raw;
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i40e_status status;
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if (!reg_val0)
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return I40E_ERR_PARAM;
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i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
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cmd_resp->address0 = cpu_to_le32(reg_addr0);
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cmd_resp->address1 = cpu_to_le32(reg_addr1);
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status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
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if (!status) {
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*reg_val0 = le32_to_cpu(cmd_resp->data0);
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if (reg_val1)
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*reg_val1 = le32_to_cpu(cmd_resp->data1);
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}
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return status;
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}
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/**
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* i40e_aq_resume_port_tx
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* @hw: pointer to the hardware structure
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@ -3417,3 +3458,79 @@ void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
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break;
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}
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}
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/**
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* i40e_read_bw_from_alt_ram
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* @hw: pointer to the hardware structure
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* @max_bw: pointer for max_bw read
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* @min_bw: pointer for min_bw read
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* @min_valid: pointer for bool that is true if min_bw is a valid value
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* @max_valid: pointer for bool that is true if max_bw is a valid value
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*
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* Read bw from the alternate ram for the given pf
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**/
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i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
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u32 *max_bw, u32 *min_bw,
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bool *min_valid, bool *max_valid)
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{
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i40e_status status;
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u32 max_bw_addr, min_bw_addr;
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/* Calculate the address of the min/max bw registers */
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max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
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I40E_ALT_STRUCT_MAX_BW_OFFSET +
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(I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
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min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
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I40E_ALT_STRUCT_MIN_BW_OFFSET +
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(I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
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/* Read the bandwidths from alt ram */
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status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
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min_bw_addr, min_bw);
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if (*min_bw & I40E_ALT_BW_VALID_MASK)
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*min_valid = true;
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else
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*min_valid = false;
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if (*max_bw & I40E_ALT_BW_VALID_MASK)
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*max_valid = true;
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else
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*max_valid = false;
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return status;
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}
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/**
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* i40e_aq_configure_partition_bw
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* @hw: pointer to the hardware structure
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* @bw_data: Buffer holding valid pfs and bw limits
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* @cmd_details: pointer to command details
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*
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* Configure partitions guaranteed/max bw
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**/
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i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
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struct i40e_aqc_configure_partition_bw_data *bw_data,
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struct i40e_asq_cmd_details *cmd_details)
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{
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i40e_status status;
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struct i40e_aq_desc desc;
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u16 bwd_size = sizeof(*bw_data);
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i40e_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_configure_partition_bw);
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/* Indirect command */
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desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
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desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
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if (bwd_size > I40E_AQ_LARGE_BUF)
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desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
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desc.datalen = cpu_to_le16(bwd_size);
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status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
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cmd_details);
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return status;
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}
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@ -7253,6 +7253,128 @@ int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
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return pf->rss_size;
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}
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/**
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* i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
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* @pf: board private structure
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**/
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i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
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{
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i40e_status status;
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bool min_valid, max_valid;
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u32 max_bw, min_bw;
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status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
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&min_valid, &max_valid);
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if (!status) {
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if (min_valid)
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pf->npar_min_bw = min_bw;
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if (max_valid)
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pf->npar_max_bw = max_bw;
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}
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return status;
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}
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/**
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* i40e_set_npar_bw_setting - Set BW settings for this PF partition
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* @pf: board private structure
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**/
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i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
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{
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struct i40e_aqc_configure_partition_bw_data bw_data;
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i40e_status status;
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/* Set the valid bit for this pf */
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bw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);
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bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
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bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
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/* Set the new bandwidths */
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status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
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return status;
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}
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/**
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* i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
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* @pf: board private structure
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**/
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i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
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{
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/* Commit temporary BW setting to permanent NVM image */
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enum i40e_admin_queue_err last_aq_status;
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i40e_status ret;
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u16 nvm_word;
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if (pf->hw.partition_id != 1) {
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dev_info(&pf->pdev->dev,
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"Commit BW only works on partition 1! This is partition %d",
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pf->hw.partition_id);
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ret = I40E_NOT_SUPPORTED;
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goto bw_commit_out;
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}
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/* Acquire NVM for read access */
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ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
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last_aq_status = pf->hw.aq.asq_last_status;
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if (ret) {
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dev_info(&pf->pdev->dev,
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"Cannot acquire NVM for read access, err %d: aq_err %d\n",
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ret, last_aq_status);
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goto bw_commit_out;
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}
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/* Read word 0x10 of NVM - SW compatibility word 1 */
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ret = i40e_aq_read_nvm(&pf->hw,
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I40E_SR_NVM_CONTROL_WORD,
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0x10, sizeof(nvm_word), &nvm_word,
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false, NULL);
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/* Save off last admin queue command status before releasing
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* the NVM
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*/
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last_aq_status = pf->hw.aq.asq_last_status;
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i40e_release_nvm(&pf->hw);
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if (ret) {
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dev_info(&pf->pdev->dev, "NVM read error, err %d aq_err %d\n",
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ret, last_aq_status);
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goto bw_commit_out;
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}
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/* Wait a bit for NVM release to complete */
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msleep(50);
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/* Acquire NVM for write access */
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ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
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last_aq_status = pf->hw.aq.asq_last_status;
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if (ret) {
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dev_info(&pf->pdev->dev,
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"Cannot acquire NVM for write access, err %d: aq_err %d\n",
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ret, last_aq_status);
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goto bw_commit_out;
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}
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/* Write it back out unchanged to initiate update NVM,
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* which will force a write of the shadow (alt) RAM to
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* the NVM - thus storing the bandwidth values permanently.
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*/
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ret = i40e_aq_update_nvm(&pf->hw,
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I40E_SR_NVM_CONTROL_WORD,
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0x10, sizeof(nvm_word),
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&nvm_word, true, NULL);
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/* Save off last admin queue command status before releasing
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* the NVM
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*/
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last_aq_status = pf->hw.aq.asq_last_status;
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i40e_release_nvm(&pf->hw);
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if (ret)
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dev_info(&pf->pdev->dev,
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"BW settings NOT SAVED, err %d aq_err %d\n",
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ret, last_aq_status);
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bw_commit_out:
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return ret;
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}
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/**
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* i40e_sw_init - Initialize general software structures (struct i40e_pf)
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* @pf: board private structure to initialize
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@ -7306,6 +7428,13 @@ static int i40e_sw_init(struct i40e_pf *pf)
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if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
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pf->flags |= I40E_FLAG_MFP_ENABLED;
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dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
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if (i40e_get_npar_bw_setting(pf))
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dev_warn(&pf->pdev->dev,
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"Could not get NPAR bw settings\n");
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else
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dev_info(&pf->pdev->dev,
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"Min BW = %8.8x, Max BW = %8.8x\n",
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pf->npar_min_bw, pf->npar_max_bw);
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}
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/* FW/NVM is not yet fixed in this regard */
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@ -1,7 +1,7 @@
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/*******************************************************************************
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*
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* Intel Ethernet Controller XL710 Family Linux Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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* Copyright(c) 2013 - 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -246,6 +246,12 @@ void i40e_clear_hw(struct i40e_hw *hw);
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void i40e_clear_pxe_mode(struct i40e_hw *hw);
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bool i40e_get_link_status(struct i40e_hw *hw);
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i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
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i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
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u32 *max_bw, u32 *min_bw, bool *min_valid,
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bool *max_valid);
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i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
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struct i40e_aqc_configure_partition_bw_data *bw_data,
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struct i40e_asq_cmd_details *cmd_details);
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i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
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i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
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u32 pba_num_size);
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@ -1401,6 +1401,19 @@ struct i40e_lldp_variables {
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u16 crc8;
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};
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/* Offsets into Alternate Ram */
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#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
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#define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
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#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
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#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
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#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
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#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
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/* Alternate Ram Bandwidth Masks */
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#define I40E_ALT_BW_VALUE_MASK 0xFF
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#define I40E_ALT_BW_RELATIVE_MASK 0x40000000
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#define I40E_ALT_BW_VALID_MASK 0x80000000
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/* RSS Hash Table Size */
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#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
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#endif /* _I40E_TYPE_H_ */
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