forked from luck/tmp_suning_uos_patched
atomics/treewide: Remove atomic_inc_not_zero_hint()
While documentation suggests atomic_inc_not_zero_hint() will perform better than atomic_inc_not_zero(), this is unlikely to be the case. No architectures implement atomic_inc_not_zero_hint() directly, and thus it either falls back to atomic_inc_not_zero(), or a loop using atomic_cmpxchg(). Whenever the hint does not match the value in memory, the repeated use of atomic_cmpxchg() will be more expensive than the read that atomic_inc_not_zero_hint() attempts to avoid. For architectures with LL/SC atomics, a read cannot be avoided, and it would always be better to use atomic_inc_not_zero() directly. For other architectures, their own atomic_inc_not_zero() is likely to be more optimal than an atomic_cmpxchg() loop regardless. Generally, atomic_inc_not_zero_hint() is liable to perform worse than atomic_inc_not_zero(). Further, atomic_inc_not_zero_hint() only exists for atomic_t, and not atomic64_t or atomic_long_t, and there is only one user in the kernel tree. Given all this, let's remove atomic_inc_not_zero_hint(), and migrate the existing user over to atomic_inc_not_zero(). There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/lkml/20180621121321.4761-4-mark.rutland@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -571,38 +571,6 @@ static inline int atomic_fetch_andnot_release(int i, atomic_t *v)
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}
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}
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#endif
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#endif
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/**
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* atomic_inc_not_zero_hint - increment if not null
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* @v: pointer of type atomic_t
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* @hint: probable value of the atomic before the increment
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*
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* This version of atomic_inc_not_zero() gives a hint of probable
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* value of the atomic. This helps processor to not read the memory
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* before doing the atomic read/modify/write cycle, lowering
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* number of bus transactions on some arches.
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*
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* Returns: 0 if increment was not done, 1 otherwise.
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*/
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#ifndef atomic_inc_not_zero_hint
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static inline int atomic_inc_not_zero_hint(atomic_t *v, int hint)
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{
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int val, c = hint;
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/* sanity test, should be removed by compiler if hint is a constant */
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if (!hint)
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return atomic_inc_not_zero(v);
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do {
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val = atomic_cmpxchg(v, c, c + 1);
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if (val == c)
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return 1;
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c = val;
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} while (c);
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return 0;
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}
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#endif
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#ifndef atomic_inc_unless_negative
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#ifndef atomic_inc_unless_negative
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static inline int atomic_inc_unless_negative(atomic_t *p)
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static inline int atomic_inc_unless_negative(atomic_t *p)
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{
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{
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@ -244,7 +244,7 @@ static int pppoatm_may_send(struct pppoatm_vcc *pvcc, int size)
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* the packet count limit, so...
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* the packet count limit, so...
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*/
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*/
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if (atm_may_send(pvcc->atmvcc, size) &&
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if (atm_may_send(pvcc->atmvcc, size) &&
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atomic_inc_not_zero_hint(&pvcc->inflight, NONE_INFLIGHT))
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atomic_inc_not_zero(&pvcc->inflight))
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return 1;
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return 1;
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/*
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/*
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