forked from luck/tmp_suning_uos_patched
x86/insn: perf tools: Add new xsave instructions
Add xsavec, xsaves and xrstors to the op code map and the perf tools new instructions test. To run the test: $ tools/perf/perf test "x86 ins" 39: Test x86 instruction decoder - new instructions : Ok Or to see the details: $ tools/perf/perf test -v "x86 ins" 2>&1 | grep 'xsave\|xrst' For information about xsavec, xsaves and xrstors, refer the Intel SDM. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Qiaowei Ren <qiaowei.ren@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1441196131-20632-8-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Adrian Hunter
Arnaldo Carvalho de Melo
parent
978260cdbe
commit
f83b6b64eb
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@ -899,6 +899,9 @@ EndTable
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GrpTable: Grp9
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1: CMPXCHG8B/16B Mq/Mdq
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3: xrstors
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4: xsavec
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5: xsaves
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6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B)
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7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B)
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EndTable
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@ -636,5 +636,23 @@
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"0f ae 30 \txsaveopt (%eax)",},
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{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
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"0f ae f0 \tmfence ",},
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{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
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"0f c7 20 \txsavec (%eax)",},
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{{0x0f, 0xc7, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
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"0f c7 25 78 56 34 12 \txsavec 0x12345678",},
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{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%eax,%ecx,8)",},
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{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
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"0f c7 28 \txsaves (%eax)",},
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{{0x0f, 0xc7, 0x2d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
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"0f c7 2d 78 56 34 12 \txsaves 0x12345678",},
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{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%eax,%ecx,8)",},
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{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
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"0f c7 18 \txrstors (%eax)",},
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{{0x0f, 0xc7, 0x1d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
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"0f c7 1d 78 56 34 12 \txrstors 0x12345678",},
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{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%eax,%ecx,8)",},
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{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
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"66 0f ae f8 \tpcommit ",},
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@ -734,5 +734,35 @@
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"41 0f ae 30 \txsaveopt (%r8)",},
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{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
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"0f ae f0 \tmfence ",},
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{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
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"0f c7 20 \txsavec (%rax)",},
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{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "",
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"41 0f c7 20 \txsavec (%r8)",},
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{{0x0f, 0xc7, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 24 25 78 56 34 12 \txsavec 0x12345678",},
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{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%rax,%rcx,8)",},
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{{0x41, 0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"41 0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%r8,%rcx,8)",},
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{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
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"0f c7 28 \txsaves (%rax)",},
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{{0x41, 0x0f, 0xc7, 0x28, }, 4, 0, "", "",
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"41 0f c7 28 \txsaves (%r8)",},
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{{0x0f, 0xc7, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 2c 25 78 56 34 12 \txsaves 0x12345678",},
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{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%rax,%rcx,8)",},
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{{0x41, 0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"41 0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%r8,%rcx,8)",},
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{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
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"0f c7 18 \txrstors (%rax)",},
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{{0x41, 0x0f, 0xc7, 0x18, }, 4, 0, "", "",
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"41 0f c7 18 \txrstors (%r8)",},
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{{0x0f, 0xc7, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 1c 25 78 56 34 12 \txrstors 0x12345678",},
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{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",},
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{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",},
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{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
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"66 0f ae f8 \tpcommit ",},
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@ -445,6 +445,30 @@ int main(void)
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asm volatile("xsaveopt (%r8)");
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asm volatile("mfence");
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/* xsavec mem */
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asm volatile("xsavec (%rax)");
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asm volatile("xsavec (%r8)");
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asm volatile("xsavec (0x12345678)");
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asm volatile("xsavec 0x12345678(%rax,%rcx,8)");
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asm volatile("xsavec 0x12345678(%r8,%rcx,8)");
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/* xsaves mem */
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asm volatile("xsaves (%rax)");
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asm volatile("xsaves (%r8)");
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asm volatile("xsaves (0x12345678)");
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asm volatile("xsaves 0x12345678(%rax,%rcx,8)");
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asm volatile("xsaves 0x12345678(%r8,%rcx,8)");
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/* xrstors mem */
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asm volatile("xrstors (%rax)");
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asm volatile("xrstors (%r8)");
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asm volatile("xrstors (0x12345678)");
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asm volatile("xrstors 0x12345678(%rax,%rcx,8)");
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asm volatile("xrstors 0x12345678(%r8,%rcx,8)");
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#else /* #ifdef __x86_64__ */
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/* bndmk m32, bnd */
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@ -822,6 +846,24 @@ int main(void)
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asm volatile("xsaveopt (%eax)");
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asm volatile("mfence");
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/* xsavec mem */
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asm volatile("xsavec (%eax)");
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asm volatile("xsavec (0x12345678)");
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asm volatile("xsavec 0x12345678(%eax,%ecx,8)");
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/* xsaves mem */
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asm volatile("xsaves (%eax)");
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asm volatile("xsaves (0x12345678)");
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asm volatile("xsaves 0x12345678(%eax,%ecx,8)");
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/* xrstors mem */
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asm volatile("xrstors (%eax)");
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asm volatile("xrstors (0x12345678)");
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asm volatile("xrstors 0x12345678(%eax,%ecx,8)");
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#endif /* #ifndef __x86_64__ */
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/* pcommit */
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@ -899,6 +899,9 @@ EndTable
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GrpTable: Grp9
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1: CMPXCHG8B/16B Mq/Mdq
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3: xrstors
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4: xsavec
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5: xsaves
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6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B)
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7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B)
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EndTable
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