AcoSail/kernel_optimize_test
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ARM: dts: sunxi: h3-h5: remove mmc0 card detection pin from pinctrl

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The GPIO card detection pin (mmc0_cd_pin) is already requested and
configured by mmc_gpiod_request_cd() in drivers/mmc/core/slot-gpio.c
so pinctrl is not needed.

Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Joonas Kylmälä 2018-02-08 14:01:38 +02:00 committed by Maxime Ripard
parent 8b8061fcbf
commit f8d5fe8fc3
No known key found for this signature in database
GPG Key ID: D2B4C094214DAF74
9 changed files with 8 additions and 14 deletions
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2
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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@ -137,7 +137,7 @@ &ir {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

2
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
View File

@ -116,7 +116,7 @@ &ir {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

2
arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
View File

@ -81,7 +81,7 @@ wifi_pwrseq: wifi_pwrseq {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

2
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
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@ -97,7 +97,7 @@ &mmc0 {
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
status = "okay";
vmmc-supply = <&reg_vcc3v3>;
};

2
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
View File

@ -133,7 +133,7 @@ &ir {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

2
arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
View File

@ -107,7 +107,7 @@ &ir {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

2
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
View File

@ -107,7 +107,7 @@ &emac {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

2
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
View File

@ -129,7 +129,7 @@ &ir {
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

6
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -356,12 +356,6 @@ mmc0_pins_a: mmc0 {
bias-pull-up;
};
mmc0_cd_pin: mmc0_cd_pin {
pins = "PF6";
function = "gpio_in";
bias-pull-up;
};
mmc1_pins_a: mmc1 {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";