forked from luck/tmp_suning_uos_patched
irqchip/renesas-intc-irqpin: Remove obsolete platform data support
Since commit 4baadb9e05
("ARM: shmobile: r8a7778: remove obsolete
setup code"), all Renesas SoCs with a renesas-intc-irqpin module are
only supported in generic DT-only ARM multi-platform builds. The driver
doesn't need to use platform data anymore, hence remove platform data
configuration.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1448376581-9202-2-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
parent
8005c49d9a
commit
f9551a9c08
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@ -31,7 +31,6 @@
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/pm_runtime.h>
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#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
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@ -75,7 +74,7 @@ struct intc_irqpin_irq {
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struct intc_irqpin_priv {
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struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
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struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
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struct renesas_intc_irqpin_config config;
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unsigned int sense_bitfield_width;
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unsigned int number_of_irqs;
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struct platform_device *pdev;
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struct irq_chip irq_chip;
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@ -171,7 +170,7 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
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static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
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{
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/* The SENSE register is assumed to be 32-bit. */
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int bitfield_width = p->config.sense_bitfield_width;
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int bitfield_width = p->sense_bitfield_width;
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int shift = 32 - (irq + 1) * bitfield_width;
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dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
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@ -378,7 +377,6 @@ MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
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static int intc_irqpin_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct renesas_intc_irqpin_config *pdata = dev->platform_data;
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const struct of_device_id *of_id;
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struct intc_irqpin_priv *p;
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struct intc_irqpin_iomem *i;
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@ -388,6 +386,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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void (*enable_fn)(struct irq_data *d);
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void (*disable_fn)(struct irq_data *d);
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const char *name = dev_name(dev);
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bool control_parent;
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int ref_irq;
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int ret;
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int k;
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@ -399,16 +398,11 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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/* deal with driver instance configuration */
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if (pdata) {
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memcpy(&p->config, pdata, sizeof(*pdata));
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} else {
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of_property_read_u32(dev->of_node, "sense-bitfield-width",
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&p->config.sense_bitfield_width);
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p->config.control_parent = of_property_read_bool(dev->of_node,
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"control-parent");
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}
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if (!p->config.sense_bitfield_width)
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p->config.sense_bitfield_width = 4; /* default to 4 bits */
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of_property_read_u32(dev->of_node, "sense-bitfield-width",
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&p->sense_bitfield_width);
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control_parent = of_property_read_bool(dev->of_node, "control-parent");
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if (!p->sense_bitfield_width)
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p->sense_bitfield_width = 4; /* default to 4 bits */
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p->pdev = pdev;
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platform_set_drvdata(pdev, p);
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@ -515,7 +509,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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/* use more severe masking method if requested */
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if (p->config.control_parent) {
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if (control_parent) {
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enable_fn = intc_irqpin_irq_enable_force;
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disable_fn = intc_irqpin_irq_disable_force;
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} else if (!p->shared_irqs) {
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@ -534,10 +528,9 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
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irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
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p->irq_domain = irq_domain_add_simple(dev->of_node,
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p->number_of_irqs,
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p->config.irq_base,
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&intc_irqpin_irq_domain_ops, p);
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p->irq_domain = irq_domain_add_simple(dev->of_node, p->number_of_irqs,
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0, &intc_irqpin_irq_domain_ops,
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p);
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if (!p->irq_domain) {
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ret = -ENXIO;
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dev_err(dev, "cannot initialize irq domain\n");
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@ -572,13 +565,6 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
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/* warn in case of mismatch if irq base is specified */
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if (p->config.irq_base) {
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if (p->config.irq_base != p->irq[0].domain_irq)
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dev_warn(dev, "irq base mismatch (%d/%d)\n",
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p->config.irq_base, p->irq[0].domain_irq);
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}
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return 0;
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err1:
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@ -1,29 +0,0 @@
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/*
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* Renesas INTC External IRQ Pin Driver
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__
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#define __IRQ_RENESAS_INTC_IRQPIN_H__
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struct renesas_intc_irqpin_config {
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unsigned int sense_bitfield_width;
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unsigned int irq_base;
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bool control_parent;
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};
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#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */
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