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ALSA: hda - use usleep_range in link reset and change timeout check

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Reducing the time on HDA link reset can help to reduce the driver loading
time. So we replace msleep with usleep_range to get more accurate time
control and change the value to a smaller one. And a 100ms timeout is set
for both entering and exiting the link reset.

Signed-off-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Mengdong Lin 2012-12-12 09:16:15 -05:00 committed by Takashi Iwai
parent 6121b84af3
commit fa348da53b
1 changed files with 11 additions and 9 deletions
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20
sound/pci/hda/hda_intel.c
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@ -1054,7 +1054,7 @@ static void azx_power_notify(struct hda_bus *bus, bool power_up);
/* reset codec link */
static int azx_reset(struct azx *chip, int full_reset)
{
int count;
unsigned long timeout;
if (!full_reset)
goto __skip;
@ -1065,24 +1065,26 @@ static int azx_reset(struct azx *chip, int full_reset)
/* reset controller */
azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
count = 50;
while (azx_readb(chip, GCTL) && --count)
msleep(1);
timeout = jiffies + msecs_to_jiffies(100);
while (azx_readb(chip, GCTL) &&
time_before(jiffies, timeout))
usleep_range(500, 1000);
/* delay for >= 100us for codec PLL to settle per spec
* Rev 0.9 section 5.5.1
*/
msleep(1);
usleep_range(500, 1000);
/* Bring controller out of reset */
azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
count = 50;
while (!azx_readb(chip, GCTL) && --count)
msleep(1);
timeout = jiffies + msecs_to_jiffies(100);
while (!azx_readb(chip, GCTL) &&
time_before(jiffies, timeout))
usleep_range(500, 1000);
/* Brent Chartrand said to wait >= 540us for codecs to initialize */
msleep(1);
usleep_range(1000, 1200);
__skip:
/* check to see if controller is ready */