forked from luck/tmp_suning_uos_patched
drm/radeon: consolidate UVD clock programming
Instead of duplicating the code over and over again, just use a single function to handle the clock calculations. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
092fbc4ca2
commit
facd112d13
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@ -989,62 +989,10 @@ int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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return r;
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}
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static int evergreen_uvd_calc_post_div(unsigned target_freq,
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unsigned vco_freq,
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unsigned *div)
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{
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/* target larger than vco frequency ? */
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if (vco_freq < target_freq)
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return -1; /* forget it */
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/* Fclk = Fvco / PDIV */
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*div = vco_freq / target_freq;
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/* we alway need a frequency less than or equal the target */
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if ((vco_freq / *div) > target_freq)
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*div += 1;
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/* dividers above 5 must be even */
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if (*div > 5 && *div % 2)
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*div += 1;
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/* out of range ? */
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if (*div >= 128)
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return -1; /* forget it */
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return vco_freq / *div;
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}
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static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev)
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{
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unsigned i;
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/* assert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
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/* wait for CTLACK and CTLACK2 to get asserted */
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for (i = 0; i < 100; ++i) {
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uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
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if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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/* deassert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
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return 0;
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}
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int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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{
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/* start off with something large */
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int optimal_diff_score = 0x7FFFFFF;
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unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
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unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
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unsigned vco_freq;
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unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
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int r;
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/* bypass vclk and dclk with bclk */
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@ -1061,40 +1009,11 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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return 0;
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}
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/* loop through vco from low to high */
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for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
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unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
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int calc_clk, diff_score, diff_vclk, diff_dclk;
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unsigned vclk_div, dclk_div;
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/* fb div out of range ? */
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if (fb_div > 0x03FFFFFF)
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break; /* it can oly get worse */
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/* calc vclk with current vco freq. */
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calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_vclk = vclk - calc_clk;
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/* calc dclk with current vco freq. */
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calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_dclk = dclk - calc_clk;
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/* determine if this vco setting is better than current optimal settings */
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diff_score = abs(diff_vclk) + abs(diff_dclk);
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if (diff_score < optimal_diff_score) {
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optimal_fb_div = fb_div;
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optimal_vclk_div = vclk_div;
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optimal_dclk_div = dclk_div;
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optimal_vco_freq = vco_freq;
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optimal_diff_score = diff_score;
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if (optimal_diff_score == 0)
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break; /* it can't get better than this */
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}
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}
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r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
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16384, 0x03FFFFFF, 0, 128, 5,
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&fb_div, &vclk_div, &dclk_div);
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if (r)
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return r;
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/* set VCO_MODE to 1 */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
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@ -1108,7 +1027,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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mdelay(1);
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r = evergreen_uvd_send_upll_ctlreq(rdev);
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r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
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if (r)
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return r;
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@ -1119,19 +1038,19 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
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/* set feedback divider */
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
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/* set ref divider to 0 */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
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if (optimal_vco_freq < 187500)
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if (fb_div < 307200)
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WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
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else
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WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
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/* set PDIV_A and PDIV_B */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
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UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
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~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
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/* give the PLL some time to settle */
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@ -1145,7 +1064,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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/* switch from bypass mode to normal mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
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r = evergreen_uvd_send_upll_ctlreq(rdev);
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r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
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if (r)
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return r;
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@ -1208,6 +1208,10 @@
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#define UVD_CONTEXT_ID 0xf6f4
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# define UPLL_CTLREQ_MASK 0x00000008
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# define UPLL_CTLACK_MASK 0x40000000
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# define UPLL_CTLACK2_MASK 0x80000000
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/*
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* PM4
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*/
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@ -1162,6 +1162,17 @@ void radeon_uvd_free_handles(struct radeon_device *rdev,
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struct drm_file *filp);
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int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
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void radeon_uvd_note_usage(struct radeon_device *rdev);
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int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
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unsigned vclk, unsigned dclk,
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unsigned vco_min, unsigned vco_max,
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unsigned fb_factor, unsigned fb_mask,
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unsigned pd_min, unsigned pd_max,
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unsigned pd_even,
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unsigned *optimal_fb_div,
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unsigned *optimal_vclk_div,
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unsigned *optimal_dclk_div);
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int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
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unsigned cg_upll_func_cntl);
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struct r600_audio {
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int channels;
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@ -692,3 +692,140 @@ void radeon_uvd_note_usage(struct radeon_device *rdev)
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if (set_clocks)
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radeon_set_uvd_clocks(rdev, 53300, 40000);
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}
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static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
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unsigned target_freq,
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unsigned pd_min,
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unsigned pd_even)
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{
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unsigned post_div = vco_freq / target_freq;
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/* adjust to post divider minimum value */
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if (post_div < pd_min)
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post_div = pd_min;
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/* we alway need a frequency less than or equal the target */
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if ((vco_freq / post_div) > target_freq)
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post_div += 1;
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/* post dividers above a certain value must be even */
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if (post_div > pd_even && post_div % 2)
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post_div += 1;
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return post_div;
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}
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/**
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* radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
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*
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* @rdev: radeon_device pointer
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* @vclk: wanted VCLK
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* @dclk: wanted DCLK
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* @vco_min: minimum VCO frequency
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* @vco_max: maximum VCO frequency
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* @fb_factor: factor to multiply vco freq with
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* @fb_mask: limit and bitmask for feedback divider
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* @pd_min: post divider minimum
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* @pd_max: post divider maximum
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* @pd_even: post divider must be even above this value
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* @optimal_fb_div: resulting feedback divider
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* @optimal_vclk_div: resulting vclk post divider
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* @optimal_dclk_div: resulting dclk post divider
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*
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* Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
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* Returns zero on success -EINVAL on error.
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*/
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int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
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unsigned vclk, unsigned dclk,
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unsigned vco_min, unsigned vco_max,
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unsigned fb_factor, unsigned fb_mask,
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unsigned pd_min, unsigned pd_max,
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unsigned pd_even,
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unsigned *optimal_fb_div,
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unsigned *optimal_vclk_div,
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unsigned *optimal_dclk_div)
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{
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unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
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/* start off with something large */
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unsigned optimal_score = ~0;
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/* loop through vco from low to high */
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vco_min = max(max(vco_min, vclk), dclk);
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for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
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uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
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unsigned vclk_div, dclk_div, score;
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do_div(fb_div, ref_freq);
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/* fb div out of range ? */
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if (fb_div > fb_mask)
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break; /* it can oly get worse */
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fb_div &= fb_mask;
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/* calc vclk divider with current vco freq */
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vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
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pd_min, pd_even);
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if (vclk_div > pd_max)
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break; /* vco is too big, it has to stop */
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/* calc dclk divider with current vco freq */
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dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
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pd_min, pd_even);
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if (vclk_div > pd_max)
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break; /* vco is too big, it has to stop */
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/* calc score with current vco freq */
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score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
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/* determine if this vco setting is better than current optimal settings */
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if (score < optimal_score) {
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*optimal_fb_div = fb_div;
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*optimal_vclk_div = vclk_div;
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*optimal_dclk_div = dclk_div;
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optimal_score = score;
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if (optimal_score == 0)
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break; /* it can't get better than this */
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}
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}
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/* did we found a valid setup ? */
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if (optimal_score == ~0)
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return -EINVAL;
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return 0;
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}
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int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
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unsigned cg_upll_func_cntl)
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{
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unsigned i;
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/* make sure UPLL_CTLREQ is deasserted */
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WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
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mdelay(10);
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/* assert UPLL_CTLREQ */
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WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
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/* wait for CTLACK and CTLACK2 to get asserted */
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for (i = 0; i < 100; ++i) {
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uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
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if ((RREG32(cg_upll_func_cntl) & mask) == mask)
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break;
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mdelay(10);
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}
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/* deassert UPLL_CTLREQ */
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WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
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if (i == 100) {
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DRM_ERROR("Timeout setting UVD clocks!\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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@ -44,56 +44,9 @@ void rv770_fini(struct radeon_device *rdev);
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static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
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int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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static int rv770_uvd_calc_post_div(unsigned target_freq,
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unsigned vco_freq,
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unsigned *div)
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{
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/* Fclk = Fvco / PDIV */
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*div = vco_freq / target_freq;
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/* we alway need a frequency less than or equal the target */
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if ((vco_freq / *div) > target_freq)
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*div += 1;
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/* out of range ? */
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if (*div > 30)
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return -1; /* forget it */
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*div -= 1;
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return vco_freq / (*div + 1);
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}
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static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev)
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{
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unsigned i;
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/* assert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
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/* wait for CTLACK and CTLACK2 to get asserted */
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for (i = 0; i < 100; ++i) {
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uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
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if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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/* deassert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
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return 0;
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}
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int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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{
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/* start off with something large */
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int optimal_diff_score = 0x7FFFFFF;
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unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
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unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
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unsigned vco_freq, vco_min = 50000, vco_max = 160000;
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unsigned ref_freq = rdev->clock.spll.reference_freq;
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unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
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int r;
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/* RV740 uses evergreen uvd clk programming */
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@ -111,44 +64,15 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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return 0;
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}
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/* loop through vco from low to high */
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vco_min = max(max(vco_min, vclk), dclk);
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for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) {
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uint64_t fb_div = (uint64_t)vco_freq * 43663;
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int calc_clk, diff_score, diff_vclk, diff_dclk;
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unsigned vclk_div, dclk_div;
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r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
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43663, 0x03FFFFFE, 1, 30, ~0,
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&fb_div, &vclk_div, &dclk_div);
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if (r)
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return r;
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do_div(fb_div, ref_freq);
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fb_div |= 1;
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/* fb div out of range ? */
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if (fb_div > 0x03FFFFFF)
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break; /* it can oly get worse */
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/* calc vclk with current vco freq. */
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calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_vclk = vclk - calc_clk;
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/* calc dclk with current vco freq. */
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calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_dclk = dclk - calc_clk;
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/* determine if this vco setting is better than current optimal settings */
|
||||
diff_score = abs(diff_vclk) + abs(diff_dclk);
|
||||
if (diff_score < optimal_diff_score) {
|
||||
optimal_fb_div = fb_div;
|
||||
optimal_vclk_div = vclk_div;
|
||||
optimal_dclk_div = dclk_div;
|
||||
optimal_vco_freq = vco_freq;
|
||||
optimal_diff_score = diff_score;
|
||||
if (optimal_diff_score == 0)
|
||||
break; /* it can't get better than this */
|
||||
}
|
||||
}
|
||||
fb_div |= 1;
|
||||
vclk_div -= 1;
|
||||
dclk_div -= 1;
|
||||
|
||||
/* set UPLL_FB_DIV to 0x50000 */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
|
||||
|
|
@ -160,7 +84,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
|
||||
|
||||
r = rv770_uvd_send_upll_ctlreq(rdev);
|
||||
r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -170,13 +94,13 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
/* set the required FB_DIV, REF_DIV, Post divder values */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_2,
|
||||
UPLL_SW_HILEN(optimal_vclk_div >> 1) |
|
||||
UPLL_SW_LOLEN((optimal_vclk_div >> 1) + (optimal_vclk_div & 1)) |
|
||||
UPLL_SW_HILEN2(optimal_dclk_div >> 1) |
|
||||
UPLL_SW_LOLEN2((optimal_dclk_div >> 1) + (optimal_dclk_div & 1)),
|
||||
UPLL_SW_HILEN(vclk_div >> 1) |
|
||||
UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
|
||||
UPLL_SW_HILEN2(dclk_div >> 1) |
|
||||
UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
|
||||
~UPLL_SW_MASK);
|
||||
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div),
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
|
||||
~UPLL_FB_DIV_MASK);
|
||||
|
||||
/* give the PLL some time to settle */
|
||||
|
|
@ -191,7 +115,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
|
||||
|
||||
r = rv770_uvd_send_upll_ctlreq(rdev);
|
||||
r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
|
|||
|
|
@ -5415,62 +5415,9 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
|
|||
return clock;
|
||||
}
|
||||
|
||||
static int si_uvd_calc_post_div(unsigned target_freq,
|
||||
unsigned vco_freq,
|
||||
unsigned *div)
|
||||
{
|
||||
/* target larger than vco frequency ? */
|
||||
if (vco_freq < target_freq)
|
||||
return -1; /* forget it */
|
||||
|
||||
/* Fclk = Fvco / PDIV */
|
||||
*div = vco_freq / target_freq;
|
||||
|
||||
/* we alway need a frequency less than or equal the target */
|
||||
if ((vco_freq / *div) > target_freq)
|
||||
*div += 1;
|
||||
|
||||
/* dividers above 5 must be even */
|
||||
if (*div > 5 && *div % 2)
|
||||
*div += 1;
|
||||
|
||||
/* out of range ? */
|
||||
if (*div >= 128)
|
||||
return -1; /* forget it */
|
||||
|
||||
return vco_freq / *div;
|
||||
}
|
||||
|
||||
static int si_uvd_send_upll_ctlreq(struct radeon_device *rdev)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
/* assert UPLL_CTLREQ */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
|
||||
|
||||
/* wait for CTLACK and CTLACK2 to get asserted */
|
||||
for (i = 0; i < 100; ++i) {
|
||||
uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
|
||||
if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
|
||||
break;
|
||||
mdelay(10);
|
||||
}
|
||||
if (i == 100)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
/* deassert UPLL_CTLREQ */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
||||
{
|
||||
/* start off with something large */
|
||||
int optimal_diff_score = 0x7FFFFFF;
|
||||
unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
|
||||
unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
|
||||
unsigned vco_freq;
|
||||
unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
|
||||
int r;
|
||||
|
||||
/* bypass vclk and dclk with bclk */
|
||||
|
|
@ -5487,40 +5434,11 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* loop through vco from low to high */
|
||||
for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
|
||||
unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
|
||||
int calc_clk, diff_score, diff_vclk, diff_dclk;
|
||||
unsigned vclk_div, dclk_div;
|
||||
|
||||
/* fb div out of range ? */
|
||||
if (fb_div > 0x03FFFFFF)
|
||||
break; /* it can oly get worse */
|
||||
|
||||
/* calc vclk with current vco freq. */
|
||||
calc_clk = si_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
|
||||
if (calc_clk == -1)
|
||||
break; /* vco is too big, it has to stop. */
|
||||
diff_vclk = vclk - calc_clk;
|
||||
|
||||
/* calc dclk with current vco freq. */
|
||||
calc_clk = si_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
|
||||
if (calc_clk == -1)
|
||||
break; /* vco is too big, it has to stop. */
|
||||
diff_dclk = dclk - calc_clk;
|
||||
|
||||
/* determine if this vco setting is better than current optimal settings */
|
||||
diff_score = abs(diff_vclk) + abs(diff_dclk);
|
||||
if (diff_score < optimal_diff_score) {
|
||||
optimal_fb_div = fb_div;
|
||||
optimal_vclk_div = vclk_div;
|
||||
optimal_dclk_div = dclk_div;
|
||||
optimal_vco_freq = vco_freq;
|
||||
optimal_diff_score = diff_score;
|
||||
if (optimal_diff_score == 0)
|
||||
break; /* it can't get better than this */
|
||||
}
|
||||
}
|
||||
r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
|
||||
16384, 0x03FFFFFF, 0, 128, 5,
|
||||
&fb_div, &vclk_div, &dclk_div);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* set RESET_ANTI_MUX to 0 */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
|
||||
|
|
@ -5537,7 +5455,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
|
||||
mdelay(1);
|
||||
|
||||
r = si_uvd_send_upll_ctlreq(rdev);
|
||||
r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -5548,19 +5466,19 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
|
||||
|
||||
/* set feedback divider */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
|
||||
|
||||
/* set ref divider to 0 */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
|
||||
|
||||
if (optimal_vco_freq < 187500)
|
||||
if (fb_div < 307200)
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
|
||||
else
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
|
||||
|
||||
/* set PDIV_A and PDIV_B */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL_2,
|
||||
UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
|
||||
UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
|
||||
~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
|
||||
|
||||
/* give the PLL some time to settle */
|
||||
|
|
@ -5574,7 +5492,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|||
/* switch from bypass mode to normal mode */
|
||||
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
|
||||
|
||||
r = si_uvd_send_upll_ctlreq(rdev);
|
||||
r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user