forked from luck/tmp_suning_uos_patched
ALSA: hda - Replace ICH6_ prefix
ICH6_ prefix doesn't mean that it's specific to ICH6 chipset but rather its generic for all HD-audio (or "Azalia") devices. Use AZX_ prefix instead to align with other constants. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai
parent
c6bf1d8e8c
commit
fb1d8ac299
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@ -155,9 +155,9 @@ static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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/* enable the position buffer */
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if (chip->get_position[0] != azx_get_pos_lpib ||
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chip->get_position[1] != azx_get_pos_lpib) {
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if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
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if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE))
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azx_writel(chip, DPLBASE,
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(u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
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(u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE);
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}
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/* set the interrupt enable bits in the descriptor control register */
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@ -975,10 +975,10 @@ static void azx_init_cmd_io(struct azx *chip)
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azx_writew(chip, CORBWP, 0);
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/* reset the corb hw read pointer */
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azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
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azx_writew(chip, CORBRP, AZX_CORBRP_RST);
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if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
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for (timeout = 1000; timeout > 0; timeout--) {
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if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
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if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST)
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break;
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udelay(1);
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}
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@ -998,7 +998,7 @@ static void azx_init_cmd_io(struct azx *chip)
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}
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/* enable corb dma */
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azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
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azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN);
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/* RIRB set up */
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chip->rirb.addr = chip->rb.addr + 2048;
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@ -1011,14 +1011,14 @@ static void azx_init_cmd_io(struct azx *chip)
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/* set the rirb size to 256 entries (ULI requires explicitly) */
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azx_writeb(chip, RIRBSIZE, 0x02);
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/* reset the rirb hw write pointer */
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azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
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azx_writew(chip, RIRBWP, AZX_RIRBWP_RST);
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/* set N=1, get RIRB response interrupt for new entry */
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if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
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azx_writew(chip, RINTCNT, 0xc0);
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else
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azx_writew(chip, RINTCNT, 1);
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/* enable rirb dma and response irq */
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azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
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azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
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spin_unlock_irq(&chip->reg_lock);
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}
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EXPORT_SYMBOL_GPL(azx_init_cmd_io);
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@ -1062,7 +1062,7 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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return -EIO;
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}
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wp++;
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wp %= ICH6_MAX_CORB_ENTRIES;
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wp %= AZX_MAX_CORB_ENTRIES;
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rp = azx_readw(chip, CORBRP);
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if (wp == rp) {
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@ -1080,7 +1080,7 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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return 0;
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}
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#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
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#define AZX_RIRB_EX_UNSOL_EV (1<<4)
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/* retrieve RIRB entry - called from interrupt handler */
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static void azx_update_rirb(struct azx *chip)
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@ -1101,7 +1101,7 @@ static void azx_update_rirb(struct azx *chip)
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while (chip->rirb.rp != wp) {
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chip->rirb.rp++;
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chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
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chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
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rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
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res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
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@ -1112,8 +1112,7 @@ static void azx_update_rirb(struct azx *chip)
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res, res_ex,
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chip->rirb.rp, wp);
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snd_BUG();
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}
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else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
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} else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
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snd_hda_queue_unsol_event(chip->bus, res, res_ex);
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else if (chip->rirb.cmds[addr]) {
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chip->rirb.res[addr] = res;
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@ -1221,7 +1220,7 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus,
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/* release CORB/RIRB */
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azx_free_cmd_io(chip);
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/* disable unsolicited responses */
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);
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return -1;
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}
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@ -1242,7 +1241,7 @@ static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
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while (timeout--) {
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/* check IRV busy bit */
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if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
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if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
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/* reuse rirb.res as the response return value */
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chip->rirb.res[addr] = azx_readl(chip, IR);
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return 0;
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@ -1266,13 +1265,13 @@ static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
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bus->rirb_error = 0;
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while (timeout--) {
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/* check ICB busy bit */
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if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
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if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
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/* Clear IRV valid bit */
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azx_writew(chip, IRS, azx_readw(chip, IRS) |
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ICH6_IRS_VALID);
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AZX_IRS_VALID);
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azx_writel(chip, IC, val);
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azx_writew(chip, IRS, azx_readw(chip, IRS) |
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ICH6_IRS_BUSY);
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AZX_IRS_BUSY);
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return azx_single_wait_for_response(chip, addr);
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}
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udelay(1);
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@ -1501,10 +1500,10 @@ void azx_enter_link_reset(struct azx *chip)
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unsigned long timeout;
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/* reset controller */
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);
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timeout = jiffies + msecs_to_jiffies(100);
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while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
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while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) &&
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time_before(jiffies, timeout))
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usleep_range(500, 1000);
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}
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@ -1515,7 +1514,7 @@ static void azx_exit_link_reset(struct azx *chip)
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{
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unsigned long timeout;
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azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
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azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET);
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timeout = jiffies + msecs_to_jiffies(100);
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while (!azx_readb(chip, GCTL) &&
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@ -1556,7 +1555,7 @@ static int azx_reset(struct azx *chip, bool full_reset)
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/* Accept unsolicited responses */
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if (!chip->single_cmd)
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
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ICH6_GCTL_UNSOL);
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AZX_GCTL_UNSOL);
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/* detect codecs */
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if (!chip->codec_mask) {
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@ -1573,7 +1572,7 @@ static void azx_int_enable(struct azx *chip)
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{
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/* enable controller CIE and GIE */
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azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
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ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
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AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
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}
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/* disable interrupts */
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@ -1594,7 +1593,7 @@ static void azx_int_disable(struct azx *chip)
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/* disable controller CIE and GIE */
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azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
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~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
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~(AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN));
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}
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/* clear interrupts */
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@ -1615,7 +1614,7 @@ static void azx_int_clear(struct azx *chip)
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azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
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/* clear int status */
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azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
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azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
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}
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/*
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@ -339,8 +339,8 @@ static char *driver_short_names[] = {
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* Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
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* The values will be lost when the display power well is disabled.
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*/
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#define ICH6_REG_EM4 0x100c
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#define ICH6_REG_EM5 0x1010
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#define AZX_REG_EM4 0x100c
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#define AZX_REG_EM5 0x1010
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struct hda_intel {
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struct azx chip;
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@ -451,7 +451,7 @@ static void azx_init_pci(struct azx *chip)
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*/
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if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
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dev_dbg(chip->card->dev, "Clearing TCSEL\n");
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update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
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update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
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}
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/* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
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@ -1529,7 +1529,7 @@ static int azx_first_init(struct azx *chip)
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NULL);
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if (p_smbus) {
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if (p_smbus->revision < 0x30)
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gcap &= ~ICH6_GCAP_64OK;
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gcap &= ~AZX_GCAP_64OK;
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pci_dev_put(p_smbus);
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}
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}
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@ -1537,7 +1537,7 @@ static int azx_first_init(struct azx *chip)
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/* disable 64bit DMA address on some devices */
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if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
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dev_dbg(card->dev, "Disabling 64bit DMA\n");
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gcap &= ~ICH6_GCAP_64OK;
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gcap &= ~AZX_GCAP_64OK;
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}
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/* disable buffer size rounding to 128-byte multiples if supported */
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@ -1553,7 +1553,7 @@ static int azx_first_init(struct azx *chip)
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}
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/* allow 64bit DMA address if supported by H/W */
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if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
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if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
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pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
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else {
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pci_set_dma_mask(pci, DMA_BIT_MASK(32));
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@ -22,82 +22,82 @@
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/*
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* registers
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*/
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#define ICH6_REG_GCAP 0x00
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#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
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#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
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#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
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#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
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#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
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#define ICH6_REG_VMIN 0x02
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#define ICH6_REG_VMAJ 0x03
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#define ICH6_REG_OUTPAY 0x04
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#define ICH6_REG_INPAY 0x06
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#define ICH6_REG_GCTL 0x08
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#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
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#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
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#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
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#define ICH6_REG_WAKEEN 0x0c
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#define ICH6_REG_STATESTS 0x0e
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#define ICH6_REG_GSTS 0x10
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#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
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#define ICH6_REG_INTCTL 0x20
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#define ICH6_REG_INTSTS 0x24
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#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
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#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
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#define ICH6_REG_SSYNC 0x38
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#define ICH6_REG_CORBLBASE 0x40
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#define ICH6_REG_CORBUBASE 0x44
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#define ICH6_REG_CORBWP 0x48
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#define ICH6_REG_CORBRP 0x4a
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#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
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#define ICH6_REG_CORBCTL 0x4c
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#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
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#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
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#define ICH6_REG_CORBSTS 0x4d
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#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
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#define ICH6_REG_CORBSIZE 0x4e
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#define AZX_REG_GCAP 0x00
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#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
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#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
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#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
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#define AZX_GCAP_ISS (15 << 8) /* # of input streams */
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#define AZX_GCAP_OSS (15 << 12) /* # of output streams */
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#define AZX_REG_VMIN 0x02
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#define AZX_REG_VMAJ 0x03
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#define AZX_REG_OUTPAY 0x04
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#define AZX_REG_INPAY 0x06
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#define AZX_REG_GCTL 0x08
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#define AZX_GCTL_RESET (1 << 0) /* controller reset */
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#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
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#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
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#define AZX_REG_WAKEEN 0x0c
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#define AZX_REG_STATESTS 0x0e
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#define AZX_REG_GSTS 0x10
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#define AZX_GSTS_FSTS (1 << 1) /* flush status */
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#define AZX_REG_INTCTL 0x20
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#define AZX_REG_INTSTS 0x24
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#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
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#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
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#define AZX_REG_SSYNC 0x38
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#define AZX_REG_CORBLBASE 0x40
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#define AZX_REG_CORBUBASE 0x44
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#define AZX_REG_CORBWP 0x48
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#define AZX_REG_CORBRP 0x4a
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#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
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#define AZX_REG_CORBCTL 0x4c
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#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
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#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
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#define AZX_REG_CORBSTS 0x4d
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#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
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#define AZX_REG_CORBSIZE 0x4e
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#define ICH6_REG_RIRBLBASE 0x50
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#define ICH6_REG_RIRBUBASE 0x54
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#define ICH6_REG_RIRBWP 0x58
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#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
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#define ICH6_REG_RINTCNT 0x5a
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#define ICH6_REG_RIRBCTL 0x5c
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#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
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#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
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#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
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#define ICH6_REG_RIRBSTS 0x5d
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#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
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#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
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#define ICH6_REG_RIRBSIZE 0x5e
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#define AZX_REG_RIRBLBASE 0x50
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#define AZX_REG_RIRBUBASE 0x54
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#define AZX_REG_RIRBWP 0x58
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#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
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#define AZX_REG_RINTCNT 0x5a
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#define AZX_REG_RIRBCTL 0x5c
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#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
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#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
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#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
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#define AZX_REG_RIRBSTS 0x5d
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#define AZX_RBSTS_IRQ (1 << 0) /* response irq */
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#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
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#define AZX_REG_RIRBSIZE 0x5e
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#define ICH6_REG_IC 0x60
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#define ICH6_REG_IR 0x64
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#define ICH6_REG_IRS 0x68
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#define ICH6_IRS_VALID (1<<1)
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#define ICH6_IRS_BUSY (1<<0)
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#define AZX_REG_IC 0x60
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#define AZX_REG_IR 0x64
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#define AZX_REG_IRS 0x68
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#define AZX_IRS_VALID (1<<1)
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#define AZX_IRS_BUSY (1<<0)
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||||
|
||||
#define ICH6_REG_DPLBASE 0x70
|
||||
#define ICH6_REG_DPUBASE 0x74
|
||||
#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
|
||||
#define AZX_REG_DPLBASE 0x70
|
||||
#define AZX_REG_DPUBASE 0x74
|
||||
#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */
|
||||
|
||||
/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
|
||||
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
|
||||
|
||||
/* stream register offsets from stream base */
|
||||
#define ICH6_REG_SD_CTL 0x00
|
||||
#define ICH6_REG_SD_STS 0x03
|
||||
#define ICH6_REG_SD_LPIB 0x04
|
||||
#define ICH6_REG_SD_CBL 0x08
|
||||
#define ICH6_REG_SD_LVI 0x0c
|
||||
#define ICH6_REG_SD_FIFOW 0x0e
|
||||
#define ICH6_REG_SD_FIFOSIZE 0x10
|
||||
#define ICH6_REG_SD_FORMAT 0x12
|
||||
#define ICH6_REG_SD_BDLPL 0x18
|
||||
#define ICH6_REG_SD_BDLPU 0x1c
|
||||
#define AZX_REG_SD_CTL 0x00
|
||||
#define AZX_REG_SD_STS 0x03
|
||||
#define AZX_REG_SD_LPIB 0x04
|
||||
#define AZX_REG_SD_CBL 0x08
|
||||
#define AZX_REG_SD_LVI 0x0c
|
||||
#define AZX_REG_SD_FIFOW 0x0e
|
||||
#define AZX_REG_SD_FIFOSIZE 0x10
|
||||
#define AZX_REG_SD_FORMAT 0x12
|
||||
#define AZX_REG_SD_BDLPL 0x18
|
||||
#define AZX_REG_SD_BDLPU 0x1c
|
||||
|
||||
/* PCI space */
|
||||
#define ICH6_PCIREG_TCSEL 0x44
|
||||
#define AZX_PCIREG_TCSEL 0x44
|
||||
|
||||
/*
|
||||
* other constants
|
||||
|
|
@ -140,13 +140,13 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
|
|||
#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
|
||||
|
||||
/* INTCTL and INTSTS */
|
||||
#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
|
||||
#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
|
||||
#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
|
||||
#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
|
||||
#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
|
||||
#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
|
||||
|
||||
/* below are so far hardcoded - should read registers in future */
|
||||
#define ICH6_MAX_CORB_ENTRIES 256
|
||||
#define ICH6_MAX_RIRB_ENTRIES 256
|
||||
#define AZX_MAX_CORB_ENTRIES 256
|
||||
#define AZX_MAX_RIRB_ENTRIES 256
|
||||
|
||||
/* driver quirks (capabilities) */
|
||||
/* bits 0-7 are used for indicating driver type */
|
||||
|
|
@ -369,29 +369,29 @@ struct azx {
|
|||
*/
|
||||
|
||||
#define azx_writel(chip, reg, value) \
|
||||
((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg))
|
||||
#define azx_readl(chip, reg) \
|
||||
((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg))
|
||||
#define azx_writew(chip, reg, value) \
|
||||
((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg))
|
||||
#define azx_readw(chip, reg) \
|
||||
((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg))
|
||||
#define azx_writeb(chip, reg, value) \
|
||||
((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg))
|
||||
#define azx_readb(chip, reg) \
|
||||
((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg))
|
||||
|
||||
#define azx_sd_writel(chip, dev, reg, value) \
|
||||
((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg))
|
||||
#define azx_sd_readl(chip, dev, reg) \
|
||||
((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg))
|
||||
#define azx_sd_writew(chip, dev, reg, value) \
|
||||
((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg))
|
||||
#define azx_sd_readw(chip, dev, reg) \
|
||||
((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg))
|
||||
#define azx_sd_writeb(chip, dev, reg, value) \
|
||||
((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg))
|
||||
#define azx_sd_readb(chip, dev, reg) \
|
||||
((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg))
|
||||
((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg))
|
||||
|
||||
#endif /* __SOUND_HDA_PRIV_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user