forked from luck/tmp_suning_uos_patched
counter: 104-quad-8: Add lock guards - generic interface
Add lock protection from race conditions to 104-quad-8 counter driver
generic interface code changes. Mutex calls used for protection.
Fixes: f1d8a071d4 ("counter: 104-quad-8: Add Generic Counter interface support")
Signed-off-by: Syed Nayyar Waris <syednwaris@gmail.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Syed Nayyar Waris
Jonathan Cameron
parent
76551a3c3d
commit
fc06926226
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@ -44,6 +44,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
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* @base: base port address of the IIO device
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*/
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struct quad8_iio {
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struct mutex lock;
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struct counter_device counter;
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unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
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unsigned int preset[QUAD8_NUM_COUNTERS];
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@ -123,6 +124,8 @@ static int quad8_read_raw(struct iio_dev *indio_dev,
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/* Borrow XOR Carry effectively doubles count range */
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*val = (borrow ^ carry) << 24;
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mutex_lock(&priv->lock);
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/* Reset Byte Pointer; transfer Counter to Output Latch */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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base_offset + 1);
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@ -130,6 +133,8 @@ static int quad8_read_raw(struct iio_dev *indio_dev,
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for (i = 0; i < 3; i++)
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*val |= (unsigned int)inb(base_offset) << (8 * i);
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mutex_unlock(&priv->lock);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_ENABLE:
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*val = priv->ab_enable[chan->channel];
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@ -160,6 +165,8 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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if ((unsigned int)val > 0xFFFFFF)
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return -EINVAL;
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mutex_lock(&priv->lock);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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@ -183,12 +190,16 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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/* Reset Error flag */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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mutex_unlock(&priv->lock);
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return 0;
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case IIO_CHAN_INFO_ENABLE:
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/* only boolean values accepted */
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if (val < 0 || val > 1)
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return -EINVAL;
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mutex_lock(&priv->lock);
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priv->ab_enable[chan->channel] = val;
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ior_cfg = val | priv->preset_enable[chan->channel] << 1;
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@ -196,11 +207,18 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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/* Load I/O control configuration */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
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mutex_unlock(&priv->lock);
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return 0;
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case IIO_CHAN_INFO_SCALE:
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mutex_lock(&priv->lock);
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/* Quadrature scaling only available in quadrature mode */
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if (!priv->quadrature_mode[chan->channel] && (val2 || val != 1))
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if (!priv->quadrature_mode[chan->channel] &&
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(val2 || val != 1)) {
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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/* Only three gain states (1, 0.5, 0.25) */
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if (val == 1 && !val2)
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@ -214,11 +232,15 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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priv->quadrature_scale[chan->channel] = 2;
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break;
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default:
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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else
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else {
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -255,6 +277,8 @@ static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
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if (preset > 0xFFFFFF)
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return -EINVAL;
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mutex_lock(&priv->lock);
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priv->preset[chan->channel] = preset;
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/* Reset Byte Pointer */
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@ -264,6 +288,8 @@ static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
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for (i = 0; i < 3; i++)
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outb(preset >> (8 * i), base_offset);
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mutex_unlock(&priv->lock);
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return len;
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}
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@ -293,6 +319,8 @@ static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
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/* Preset enable is active low in Input/Output Control register */
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preset_enable = !preset_enable;
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mutex_lock(&priv->lock);
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priv->preset_enable[chan->channel] = preset_enable;
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ior_cfg = priv->ab_enable[chan->channel] |
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@ -301,6 +329,8 @@ static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
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/* Load I/O control configuration to Input / Output Control Register */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return len;
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}
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@ -358,6 +388,8 @@ static int quad8_set_count_mode(struct iio_dev *indio_dev,
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unsigned int mode_cfg = cnt_mode << 1;
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const int base_offset = priv->base + 2 * chan->channel + 1;
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mutex_lock(&priv->lock);
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priv->count_mode[chan->channel] = cnt_mode;
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/* Add quadrature mode configuration */
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@ -367,6 +399,8 @@ static int quad8_set_count_mode(struct iio_dev *indio_dev,
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -394,19 +428,26 @@ static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, unsigned int synchronous_mode)
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{
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struct quad8_iio *const priv = iio_priv(indio_dev);
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const unsigned int idr_cfg = synchronous_mode |
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priv->index_polarity[chan->channel] << 1;
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const int base_offset = priv->base + 2 * chan->channel + 1;
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unsigned int idr_cfg = synchronous_mode;
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mutex_lock(&priv->lock);
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idr_cfg |= priv->index_polarity[chan->channel] << 1;
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/* Index function must be non-synchronous in non-quadrature mode */
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if (synchronous_mode && !priv->quadrature_mode[chan->channel])
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if (synchronous_mode && !priv->quadrature_mode[chan->channel]) {
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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priv->synchronous_mode[chan->channel] = synchronous_mode;
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -434,8 +475,12 @@ static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, unsigned int quadrature_mode)
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{
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struct quad8_iio *const priv = iio_priv(indio_dev);
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unsigned int mode_cfg = priv->count_mode[chan->channel] << 1;
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const int base_offset = priv->base + 2 * chan->channel + 1;
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unsigned int mode_cfg;
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mutex_lock(&priv->lock);
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mode_cfg = priv->count_mode[chan->channel] << 1;
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if (quadrature_mode)
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mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
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@ -453,6 +498,8 @@ static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -480,15 +527,20 @@ static int quad8_set_index_polarity(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, unsigned int index_polarity)
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{
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struct quad8_iio *const priv = iio_priv(indio_dev);
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const unsigned int idr_cfg = priv->synchronous_mode[chan->channel] |
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index_polarity << 1;
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const int base_offset = priv->base + 2 * chan->channel + 1;
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unsigned int idr_cfg = index_polarity << 1;
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mutex_lock(&priv->lock);
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idr_cfg |= priv->synchronous_mode[chan->channel];
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priv->index_polarity[chan->channel] = index_polarity;
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -589,7 +641,7 @@ static int quad8_signal_read(struct counter_device *counter,
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static int quad8_count_read(struct counter_device *counter,
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struct counter_count *count, unsigned long *val)
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{
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const struct quad8_iio *const priv = counter->priv;
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struct quad8_iio *const priv = counter->priv;
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const int base_offset = priv->base + 2 * count->id;
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unsigned int flags;
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unsigned int borrow;
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@ -603,6 +655,8 @@ static int quad8_count_read(struct counter_device *counter,
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/* Borrow XOR Carry effectively doubles count range */
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*val = (unsigned long)(borrow ^ carry) << 24;
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mutex_lock(&priv->lock);
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/* Reset Byte Pointer; transfer Counter to Output Latch */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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base_offset + 1);
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@ -610,13 +664,15 @@ static int quad8_count_read(struct counter_device *counter,
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for (i = 0; i < 3; i++)
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*val |= (unsigned long)inb(base_offset) << (8 * i);
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mutex_unlock(&priv->lock);
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return 0;
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}
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static int quad8_count_write(struct counter_device *counter,
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struct counter_count *count, unsigned long val)
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{
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const struct quad8_iio *const priv = counter->priv;
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struct quad8_iio *const priv = counter->priv;
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const int base_offset = priv->base + 2 * count->id;
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int i;
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@ -624,6 +680,8 @@ static int quad8_count_write(struct counter_device *counter,
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if (val > 0xFFFFFF)
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return -EINVAL;
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mutex_lock(&priv->lock);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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@ -647,6 +705,8 @@ static int quad8_count_write(struct counter_device *counter,
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/* Reset Error flag */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -667,13 +727,13 @@ static enum counter_count_function quad8_count_functions_list[] = {
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static int quad8_function_get(struct counter_device *counter,
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struct counter_count *count, size_t *function)
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{
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const struct quad8_iio *const priv = counter->priv;
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struct quad8_iio *const priv = counter->priv;
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const int id = count->id;
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const unsigned int quadrature_mode = priv->quadrature_mode[id];
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const unsigned int scale = priv->quadrature_scale[id];
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if (quadrature_mode)
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switch (scale) {
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mutex_lock(&priv->lock);
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if (priv->quadrature_mode[id])
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switch (priv->quadrature_scale[id]) {
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case 0:
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*function = QUAD8_COUNT_FUNCTION_QUADRATURE_X1;
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break;
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@ -687,6 +747,8 @@ static int quad8_function_get(struct counter_device *counter,
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else
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*function = QUAD8_COUNT_FUNCTION_PULSE_DIRECTION;
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -697,10 +759,15 @@ static int quad8_function_set(struct counter_device *counter,
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const int id = count->id;
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unsigned int *const quadrature_mode = priv->quadrature_mode + id;
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unsigned int *const scale = priv->quadrature_scale + id;
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unsigned int mode_cfg = priv->count_mode[id] << 1;
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unsigned int *const synchronous_mode = priv->synchronous_mode + id;
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const unsigned int idr_cfg = priv->index_polarity[id] << 1;
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const int base_offset = priv->base + 2 * id + 1;
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unsigned int mode_cfg;
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unsigned int idr_cfg;
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mutex_lock(&priv->lock);
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mode_cfg = priv->count_mode[id] << 1;
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idr_cfg = priv->index_polarity[id] << 1;
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if (function == QUAD8_COUNT_FUNCTION_PULSE_DIRECTION) {
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*quadrature_mode = 0;
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@ -736,6 +803,8 @@ static int quad8_function_set(struct counter_device *counter,
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -852,15 +921,20 @@ static int quad8_index_polarity_set(struct counter_device *counter,
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{
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struct quad8_iio *const priv = counter->priv;
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const size_t channel_id = signal->id - 16;
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const unsigned int idr_cfg = priv->synchronous_mode[channel_id] |
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index_polarity << 1;
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const int base_offset = priv->base + 2 * channel_id + 1;
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unsigned int idr_cfg = index_polarity << 1;
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mutex_lock(&priv->lock);
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idr_cfg |= priv->synchronous_mode[channel_id];
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priv->index_polarity[channel_id] = index_polarity;
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -887,19 +961,26 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
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{
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struct quad8_iio *const priv = counter->priv;
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const size_t channel_id = signal->id - 16;
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const unsigned int idr_cfg = synchronous_mode |
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priv->index_polarity[channel_id] << 1;
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const int base_offset = priv->base + 2 * channel_id + 1;
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unsigned int idr_cfg = synchronous_mode;
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mutex_lock(&priv->lock);
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idr_cfg |= priv->index_polarity[channel_id] << 1;
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/* Index function must be non-synchronous in non-quadrature mode */
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if (synchronous_mode && !priv->quadrature_mode[channel_id])
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if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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priv->synchronous_mode[channel_id] = synchronous_mode;
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -964,6 +1045,8 @@ static int quad8_count_mode_set(struct counter_device *counter,
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break;
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}
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mutex_lock(&priv->lock);
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priv->count_mode[count->id] = cnt_mode;
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/* Set count mode configuration value */
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@ -976,6 +1059,8 @@ static int quad8_count_mode_set(struct counter_device *counter,
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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mutex_unlock(&priv->lock);
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return 0;
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}
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@ -1017,6 +1102,8 @@ static ssize_t quad8_count_enable_write(struct counter_device *counter,
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if (err)
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return err;
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mutex_lock(&priv->lock);
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priv->ab_enable[count->id] = ab_enable;
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ior_cfg = ab_enable | priv->preset_enable[count->id] << 1;
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@ -1024,6 +1111,8 @@ static ssize_t quad8_count_enable_write(struct counter_device *counter,
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/* Load I/O control configuration */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
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mutex_unlock(&priv->lock);
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return len;
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}
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@ -1052,14 +1141,28 @@ static ssize_t quad8_count_preset_read(struct counter_device *counter,
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return sprintf(buf, "%u\n", priv->preset[count->id]);
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}
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static void quad8_preset_register_set(struct quad8_iio *quad8iio, int id,
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unsigned int preset)
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{
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const unsigned int base_offset = quad8iio->base + 2 * id;
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int i;
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quad8iio->preset[id] = preset;
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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|
||||
/* Set Preset Register */
|
||||
for (i = 0; i < 3; i++)
|
||||
outb(preset >> (8 * i), base_offset);
|
||||
}
|
||||
|
||||
static ssize_t quad8_count_preset_write(struct counter_device *counter,
|
||||
struct counter_count *count, void *private, const char *buf, size_t len)
|
||||
{
|
||||
struct quad8_iio *const priv = counter->priv;
|
||||
const int base_offset = priv->base + 2 * count->id;
|
||||
unsigned int preset;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
ret = kstrtouint(buf, 0, &preset);
|
||||
if (ret)
|
||||
|
|
@ -1069,14 +1172,11 @@ static ssize_t quad8_count_preset_write(struct counter_device *counter,
|
|||
if (preset > 0xFFFFFF)
|
||||
return -EINVAL;
|
||||
|
||||
priv->preset[count->id] = preset;
|
||||
mutex_lock(&priv->lock);
|
||||
|
||||
/* Reset Byte Pointer */
|
||||
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
||||
quad8_preset_register_set(priv, count->id, preset);
|
||||
|
||||
/* Set Preset Register */
|
||||
for (i = 0; i < 3; i++)
|
||||
outb(preset >> (8 * i), base_offset);
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
|
@ -1084,15 +1184,20 @@ static ssize_t quad8_count_preset_write(struct counter_device *counter,
|
|||
static ssize_t quad8_count_ceiling_read(struct counter_device *counter,
|
||||
struct counter_count *count, void *private, char *buf)
|
||||
{
|
||||
const struct quad8_iio *const priv = counter->priv;
|
||||
struct quad8_iio *const priv = counter->priv;
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
|
||||
/* Range Limit and Modulo-N count modes use preset value as ceiling */
|
||||
switch (priv->count_mode[count->id]) {
|
||||
case 1:
|
||||
case 3:
|
||||
return quad8_count_preset_read(counter, count, private, buf);
|
||||
mutex_unlock(&priv->lock);
|
||||
return sprintf(buf, "%u\n", priv->preset[count->id]);
|
||||
}
|
||||
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
/* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
|
||||
return sprintf(buf, "33554431\n");
|
||||
}
|
||||
|
|
@ -1101,15 +1206,29 @@ static ssize_t quad8_count_ceiling_write(struct counter_device *counter,
|
|||
struct counter_count *count, void *private, const char *buf, size_t len)
|
||||
{
|
||||
struct quad8_iio *const priv = counter->priv;
|
||||
unsigned int ceiling;
|
||||
int ret;
|
||||
|
||||
ret = kstrtouint(buf, 0, &ceiling);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Only 24-bit values are supported */
|
||||
if (ceiling > 0xFFFFFF)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
|
||||
/* Range Limit and Modulo-N count modes use preset value as ceiling */
|
||||
switch (priv->count_mode[count->id]) {
|
||||
case 1:
|
||||
case 3:
|
||||
return quad8_count_preset_write(counter, count, private, buf,
|
||||
len);
|
||||
quad8_preset_register_set(priv, count->id, ceiling);
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
|
|
@ -1137,6 +1256,8 @@ static ssize_t quad8_count_preset_enable_write(struct counter_device *counter,
|
|||
/* Preset enable is active low in Input/Output Control register */
|
||||
preset_enable = !preset_enable;
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
|
||||
priv->preset_enable[count->id] = preset_enable;
|
||||
|
||||
ior_cfg = priv->ab_enable[count->id] | (unsigned int)preset_enable << 1;
|
||||
|
|
@ -1144,6 +1265,8 @@ static ssize_t quad8_count_preset_enable_write(struct counter_device *counter,
|
|||
/* Load I/O control configuration to Input / Output Control Register */
|
||||
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
|
||||
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
|
|
@ -1429,6 +1552,9 @@ static int quad8_probe(struct device *dev, unsigned int id)
|
|||
quad8iio->counter.priv = quad8iio;
|
||||
quad8iio->base = base[id];
|
||||
|
||||
/* Initialize mutex */
|
||||
mutex_init(&quad8iio->lock);
|
||||
|
||||
/* Reset all counters and disable interrupt function */
|
||||
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
|
||||
/* Set initial configuration for all counters */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user