forked from luck/tmp_suning_uos_patched
clk: ti: add clkctrl data omap5 sgx
Looks like we have sgx clock missing currently so let's add it. Cc: Adam Ford <aford173@gmail.com> Cc: Filip Matijević <filip.matijevic.pz@gmail.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: moaz korena <moaz@korena.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Cc: Philipp Rossak <embed3d@gmail.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst =
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{ 0 },
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};
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static const char * const omap5_gpu_core_mux_parents[] __initconst = {
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"dpll_core_h14x2_ck",
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"dpll_per_h14x2_ck",
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NULL,
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};
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static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
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"dpll_core_h14x2_ck",
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"dpll_per_h14x2_ck",
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NULL,
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};
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static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
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"sys_clkin",
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NULL,
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};
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static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
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.max_div = 2,
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};
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static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
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{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
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{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
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{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
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{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
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{ 0 },
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};
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static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
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"func_128m_clk",
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"dpll_per_m2x2_ck",
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@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
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{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
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{ 0x4a009020, omap5_l4per_clkctrl_regs },
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{ 0x4a009420, omap5_dss_clkctrl_regs },
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{ 0x4a009520, omap5_gpu_clkctrl_regs },
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{ 0x4a009620, omap5_l3init_clkctrl_regs },
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{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
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{ 0 },
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@ -89,6 +89,9 @@
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/* dss clocks */
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#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* gpu clocks */
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#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* l3init clocks */
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#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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