TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the bindings for the Amlogic Everything-Else power domains,
controlling the Everything-Else peripherals power domains.
The bindings targets the Amlogic G12A and SM1 compatible SoCs,
support for earlier SoCs will be added later.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
On the Turris Mox router different modules can be connected to the main
CPU board: currently a module with a SFP cage, a module with MiniPCIe
connector, a PCIe pass-through MiniPCIe connector module, a 4-port
switch module, an 8-port switch module, and a 4-port USB3 module.
For example:
[CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]
Each of this modules has an input and output shift register, and these
are connected via SPI to the CPU board.
Via SPI we are able to discover which modules are connected, in which
order, and we can also read some information about the modules (eg.
their interrupt status), and configure them.
From each module 8 bits can be read (of which low 4 bits identify the
module) and 8 bits can be written.
For example from the module with a SFP cage we can read the LOS,
TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and
RATE-SELECT signals.
This driver creates a new bus type, called "moxtet". For each Mox module
it finds via SPI, it creates a new device on the moxtet bus so that
drivers can be written for them.
It also implements a virtual interrupt controller for the modules which
send their interrupt status over the SPI shift register. These modules
do this in addition to sending their interrupt status via the shared
interrupt line. When the shared interrupt is triggered, we read from the
shift register and handle IRQs for all devices which are in interrupt.
The topology of how Mox modules are connected can then be read by
listing /sys/bus/moxtet/devices.
Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.cz
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Some of the mipi dsi resets were called
IMX8MQ_RESET_MIPI_DIS__
instead of
IMX8MQ_RESET_MIPI_DSI__
Since they're DSI related this looks like a typo. This fixes the
only in tree user as well to not break bisecting.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MM.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM Mali
GPU devices added to device trees, since the DRM drivers have now been
merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Polish and fixes for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now at
feature parity with TX1
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Devicetree updates from Olof Johansson:
"We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM
Mali GPU devices added to device trees, since the DRM drivers have now
been merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Fixes and polish for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now
at feature parity with TX1"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (586 commits)
ARM: dts: gemini: Set DIR-685 SPI CS as active low
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family
ARM: dts: exynos: Move Mali400 GPU node to "/soc"
ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210
arm64: dts: qcom: qcs404: Add missing space for cooling-cells property
arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire
arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs
arm64: dts: rockchip: enable rk3328 watchdog clock
ARM: dts: rockchip: add display nodes for rk322x
ARM: dts: rockchip: fix vop iommu-cells on rk322x
arm64: dts: rockchip: Add support for Hugsun X99 TV Box
arm64: dts: rockchip: Define values for the IPA governor for rock960
arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi
arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance.
Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
arm64: dts: qcom: sdm845-cheza: add initial cheza dt
ARM: dts: msm8974-FP2: Add vibration motor
...
Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
reset: remove redundant null check on pointer dev
soc: rockchip: work around clang warning
dt-bindings: reset: imx7: Fix the spelling of 'indices'
soc: imx: Add i.MX8MN SoC driver support
soc: aspeed: lpc-ctrl: Fix probe error handling
soc: qcom: geni: Add support for ACPI
firmware: ti_sci: Fix gcc unused-but-set-variable warning
firmware: ti_sci: Use the correct style for SPDX License Identifier
soc: imx8: Use existing of_root directly
soc: imx8: Fix potential kernel dump in error path
firmware/psci: psci_checker: Park kthreads before stopping them
memory: move jedec_ddr.h from include/memory to drivers/memory/
memory: move jedec_ddr_data.c from lib/ to drivers/memory/
MAINTAINERS: Remove myself as qcom maintainer
soc: aspeed: lpc-ctrl: make parameter optional
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
memory: tegra: Fix -Wunused-const-variable
firmware: tegra: Early resume BPMP
soc/tegra: Select pinctrl for Tegra194
...
side. The two main highlights in the core framework are the addition of an bulk
clk_get API that handles optional clks and an extra debugfs file that tells the
developer about the current parent of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is mostly
because that SoC has started converting to the clk_hw style of clk
registration. The next big update is in the Amlogic meson clk driver that
gained some support for audio, cpu, and temperature clks while fixing some PLL
issues. Finally, the biggest thing that stands out is the conversion of a large
part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
less strings and more pointer comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks here and
there to clk data along with the normal addition of a handful of new drivers
and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
- Support gated clk controller on MIPS based BCM63XX SoCs
- Small frequency support for SiLabs Si544 chips
- Support SiLabs Si5341 and Si5340 chips
* clk-bcm63xx:
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
* clk-silabs:
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
* clk-lochnagar:
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: lochnagar: Use new parent_data approach to register clock parents
* clk-rockchip:
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
clk: rockchip: add a type from SGRF-controlled gate clocks
clk: rockchip: Remove 48 MHz PLL rate from rk3288
clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
clk: rockchip: Don't yell about bad mmc phases when getting
clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
* clk-ti:
clk: ti: Use int to check return value from of_property_count_elems_of_size()
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: probe clocks from DT instead of firmware
clk: keystone: sci-clk: split out the fw clock parsing to own function
clk: keystone: sci-clk: cut down the clock name length
* clk-samsung:
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: exynos5433: Use of_clk_get_parent_count()
* clk-imx: (38 commits)
clk: imx8mq: Keep uart clocks on during system boot
clk: imx: Remove __init for imx_register_uart_clocks() API
clk: imx6q: fix section mismatch warning
clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
clk: imx8mq: Use imx_check_clocks() API directly
clk: imx: Remove __init for imx_check_clocks() API
clk: imx6sll: Switch to clk_hw based API
clk: imx7d: Switch to clk_hw based API
clk: imx6ul: Switch to clk_hw based API
clk: imx6sx: Switch to clk_hw based API
clk: imx6q: Switch to clk_hw based API
clk: imx6sl: Switch to clk_hw based API
clk: imx: Switch wrappers to clk_hw based API
clk: imx: clk-fixup-mux: Switch to clk_hw based API
clk: imx: clk-fixup-div: Switch to clk_hw based API
clk: imx: clk-gate-exclusive: Switch to clk_hw based API
clk: imx: clk-pfd: Switch to clk_hw based API
clk: imx: clk-pllv3: Switch to clk_hw based API
clk: imx: clk-gate2: Switch to clk_hw based API
clk: imx: clk-cpu: Switch to clk_hw based API
...
* clk-allwinner: (29 commits)
clk: Simplify debugfs printing and add a newline
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
...
Pull networking updates from David Miller:
"Some highlights from this development cycle:
1) Big refactoring of ipv6 route and neigh handling to support
nexthop objects configurable as units from userspace. From David
Ahern.
2) Convert explored_states in BPF verifier into a hash table,
significantly decreased state held for programs with bpf2bpf
calls, from Alexei Starovoitov.
3) Implement bpf_send_signal() helper, from Yonghong Song.
4) Various classifier enhancements to mvpp2 driver, from Maxime
Chevallier.
5) Add aRFS support to hns3 driver, from Jian Shen.
6) Fix use after free in inet frags by allocating fqdirs dynamically
and reworking how rhashtable dismantle occurs, from Eric Dumazet.
7) Add act_ctinfo packet classifier action, from Kevin
Darbyshire-Bryant.
8) Add TFO key backup infrastructure, from Jason Baron.
9) Remove several old and unused ISDN drivers, from Arnd Bergmann.
10) Add devlink notifications for flash update status to mlxsw driver,
from Jiri Pirko.
11) Lots of kTLS offload infrastructure fixes, from Jakub Kicinski.
12) Add support for mv88e6250 DSA chips, from Rasmus Villemoes.
13) Various enhancements to ipv6 flow label handling, from Eric
Dumazet and Willem de Bruijn.
14) Support TLS offload in nfp driver, from Jakub Kicinski, Dirk van
der Merwe, and others.
15) Various improvements to axienet driver including converting it to
phylink, from Robert Hancock.
16) Add PTP support to sja1105 DSA driver, from Vladimir Oltean.
17) Add mqprio qdisc offload support to dpaa2-eth, from Ioana
Radulescu.
18) Add devlink health reporting to mlx5, from Moshe Shemesh.
19) Convert stmmac over to phylink, from Jose Abreu.
20) Add PTP PHC (Physical Hardware Clock) support to mlxsw, from
Shalom Toledo.
21) Add nftables SYNPROXY support, from Fernando Fernandez Mancera.
22) Convert tcp_fastopen over to use SipHash, from Ard Biesheuvel.
23) Track spill/fill of constants in BPF verifier, from Alexei
Starovoitov.
24) Support bounded loops in BPF, from Alexei Starovoitov.
25) Various page_pool API fixes and improvements, from Jesper Dangaard
Brouer.
26) Just like ipv4, support ref-countless ipv6 route handling. From
Wei Wang.
27) Support VLAN offloading in aquantia driver, from Igor Russkikh.
28) Add AF_XDP zero-copy support to mlx5, from Maxim Mikityanskiy.
29) Add flower GRE encap/decap support to nfp driver, from Pieter
Jansen van Vuuren.
30) Protect against stack overflow when using act_mirred, from John
Hurley.
31) Allow devmap map lookups from eBPF, from Toke Høiland-Jørgensen.
32) Use page_pool API in netsec driver, Ilias Apalodimas.
33) Add Google gve network driver, from Catherine Sullivan.
34) More indirect call avoidance, from Paolo Abeni.
35) Add kTLS TX HW offload support to mlx5, from Tariq Toukan.
36) Add XDP_REDIRECT support to bnxt_en, from Andy Gospodarek.
37) Add MPLS manipulation actions to TC, from John Hurley.
38) Add sending a packet to connection tracking from TC actions, and
then allow flower classifier matching on conntrack state. From
Paul Blakey.
39) Netfilter hw offload support, from Pablo Neira Ayuso"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (2080 commits)
net/mlx5e: Return in default case statement in tx_post_resync_params
mlx5: Return -EINVAL when WARN_ON_ONCE triggers in mlx5e_tls_resync().
net: dsa: add support for BRIDGE_MROUTER attribute
pkt_sched: Include const.h
net: netsec: remove static declaration for netsec_set_tx_de()
net: netsec: remove superfluous if statement
netfilter: nf_tables: add hardware offload support
net: flow_offload: rename tc_cls_flower_offload to flow_cls_offload
net: flow_offload: add flow_block_cb_is_busy() and use it
net: sched: remove tcf block API
drivers: net: use flow block API
net: sched: use flow block API
net: flow_offload: add flow_block_cb_{priv, incref, decref}()
net: flow_offload: add list handling functions
net: flow_offload: add flow_block_cb_alloc() and flow_block_cb_free()
net: flow_offload: rename TCF_BLOCK_BINDER_TYPE_* to FLOW_BLOCK_BINDER_TYPE_*
net: flow_offload: rename TC_BLOCK_{UN}BIND to FLOW_BLOCK_{UN}BIND
net: flow_offload: add flow_block_cb_setup_simple()
net: hisilicon: Add an tx_desc to adapt HI13X1_GMAC
net: hisilicon: Add an rx_desc to adapt HI13X1_GMAC
...
This tag adds support for the Bitmain BM1880 reset controller to the
reset-simple driver and fixes a spelling mistake in the i.MX7 reset
controller binding document.
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Merge tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller changes for v5.3
This tag adds support for the Bitmain BM1880 reset controller to the
reset-simple driver and fixes a spelling mistake in the i.MX7 reset
controller binding document.
* tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux:
dt-bindings: reset: imx7: Fix the spelling of 'indices'
reset: Add reset controller support for BM1880 SoC
dt-bindings: reset: Add devicetree binding for BM1880 reset controller
Link: https://lore.kernel.org/r/1562236632.6641.14.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
for rk3288-veyron boards.
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Merge tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Display support for rk3228/rk3229 (up to hdmi output) and more love
for rk3288-veyron boards.
* tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add display nodes for rk322x
ARM: dts: rockchip: fix vop iommu-cells on rk322x
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron
Signed-off-by: Olof Johansson <olof@lixom.net>
The fixes have no functional impact:
- Fix some comment text in the memory management vmalloc_fault path.
- Fix some warnings from the DT compiler in our newly-added DT files.
- Change the newly-added DT bindings such that SoC IP blocks with
external I/O are marked as "disabled" by default, then enable them
explicitly in board DT files when the devices are used on the board.
This aligns the bindings with existing upstream practice.
- Add the MIT license as an option for a minor header file, at the
request of one of the U-Boot maintainers.
The RISC-V defconfig update builds the SiFive SPI driver and the
MMC-SPI driver by default. The intention here is to make v5.2 more
usable for testers and users with RISC-V hardware.
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Merge tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley:
"Minor RISC-V fixes and one defconfig update.
The fixes have no functional impact:
- Fix some comment text in the memory management vmalloc_fault path.
- Fix some warnings from the DT compiler in our newly-added DT files.
- Change the newly-added DT bindings such that SoC IP blocks with
external I/O are marked as "disabled" by default, then enable them
explicitly in board DT files when the devices are used on the
board. This aligns the bindings with existing upstream practice.
- Add the MIT license as an option for a minor header file, at the
request of one of the U-Boot maintainers.
The RISC-V defconfig update builds the SiFive SPI driver and the
MMC-SPI driver by default. The intention here is to make v5.2 more
usable for testers and users with RISC-V hardware"
* tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: mm: Fix code comment
dt-bindings: clock: sifive: add MIT license as an option for the header file
dt-bindings: riscv: resolve 'make dt_binding_check' warnings
riscv: dts: Re-organize the DT nodes
RISC-V: defconfig: enable MMC & SPI for RISC-V
The new route handling in ip_mc_finish_output() from 'net' overlapped
with the new support for returning congestion notifications from BPF
programs.
In order to handle this I had to take the dev_loopback_xmit() calls
out of the switch statement.
The aquantia driver conflicts were simple overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
- Do a DT/firmware lookup in clk_core_get() even when the DT index is a
nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of clk driver fixes and one core framework fix
- Do a DT/firmware lookup in clk_core_get() even when the DT index is
a nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: socfpga: stratix10: fix divider entry for the emac clocks
clk: Do a DT parent lookup even when index < 0
clk: tegra210: Fix default rates for HDA clocks
clk: ti: clkctrl: Fix returning uninitialized data
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
Add the needed clock id to enable clock settings from devicetree.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Justin Swartz <justin.swartz@risingedge.co.za>
At Bin Meng's request, add the MIT license as an option for the SiFive
FU540 PRCI header file.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
The madera driver was merged too late to catch Thomas Gleixner's cleanup
of the SPDX headers tree wide. Update the headers to match what was done
in that patch.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Add ACPI support to Qualcomm GENI SE
* Update Qualcomm Maintainers entry to remove David Brown as maintainer and
fixup typos and incorrect DT file entry
* Fixup APR domain id usage and making callbacks in non-atomic context
* Add AOSS QMP driver and bindings
* Add power domains for MSM8998 and QCS404 in QCOM RPMPD
* Add corner macros, max state support, and fixups for setting performance state
for Qcom RPMPD
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Merge tag 'qcom-drivers-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm ARM Based Driver Updates for v5.3
* Add ACPI support to Qualcomm GENI SE
* Update Qualcomm Maintainers entry to remove David Brown as maintainer and
fixup typos and incorrect DT file entry
* Fixup APR domain id usage and making callbacks in non-atomic context
* Add AOSS QMP driver and bindings
* Add power domains for MSM8998 and QCS404 in QCOM RPMPD
* Add corner macros, max state support, and fixups for setting performance state
for Qcom RPMPD
* tag 'qcom-drivers-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
soc: qcom: geni: Add support for ACPI
MAINTAINERS: Remove myself as qcom maintainer
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
soc: qcom: Add AOSS QMP driver
dt-bindings: soc: qcom: Add AOSS QMP binding
qcom: apr: Make apr callbacks in non-atomic context
soc: qcom: rpmpd: Add MSM8998 power-domains
dt-bindings: power: Add rpm power domain bindings for msm8998
soc: qcom: rpmpd: Add QCS404 power-domains
dt-bindings: power: Add rpm power domain bindings for qcs404
soc: qcom: rpmpd: Modify corner defining macros
soc: qcom: rpmpd: Add support to set rpmpd state to max
soc: qcom: rpmpd: fixup rpmpd set performance state
MAINTAINER: Fix Qualcomm ETHQOS ethernet DT file
MAINTAINERS: fix typo in file name
Signed-off-by: Olof Johansson <olof@lixom.net>
- This is a set of device tree changes with new clocks - adding
clock info for i.MX8 GPIO and SNVS RTC device.
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Merge tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT changes with new clock for 5.3:
- This is a set of device tree changes with new clocks - adding
clock info for i.MX8 GPIO and SNVS RTC device.
* tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq: add clock for SNVS RTC node
arm64: dts: imx8mm: add clock for SNVS RTC node
arm64: dts: imx8mm: add clock for GPIO node
clk: imx8m: Add GIC clock
dt-bindings: clock: imx8m: Add GIC clock
clk: imx8mm: add SNVS clock to clock tree
dt-bindings: clock: imx8mm: Add SNVS clock
clk: imx8mq: add SNVS clock to clock tree
dt-bindings: clock: imx8mq: Add SNVS clock
clk: imx8mm: add GPIO clocks to clock tree
dt-bindings: clock: imx8mm: Add GPIO clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.
Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.
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Merge tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.3-rc1
This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.
Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.
* tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits)
arm64: tegra: Enable PCIe slots in P2972-0000 board
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Add PEX DPD states as pinctrl properties
arm64: tegra: Enable ACONNECT, ADMA and AGIC
arm64: tegra: Add ACONNECT, ADMA and AGIC nodes
arm64: tegra: Sort device tree nodes alphabetically
arm64: tegra: Fix Jetson Nano GPU regulator
arm64: tegra: Update Jetson TX1 GPU regulator timings
arm64: tegra: Fix AGIC register range
arm64: tegra: Add INA3221 channel info for Jetson TX2
arm64: tegra: Enable PWM on Jetson Nano
arm64: tegra: Enable CPU sleep on Jetson Nano
arm64: tegra: Add ID EEPROMs on Jetson Nano
arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit
arm64: tegra: Add ID EEPROM for Jetson TX2 module
arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit
arm64: tegra: Add ID EEPROM for Jetson TX1 module
arm64: tegra: Don't use architected timer for suspend on Tegra210
arm64: tegra: Mark architected timer as always on
arm64: tegra: Add pin control states for I2C on Tegra186
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The Cirrus Logic Madera codecs are a family of related codecs with
extensive digital and analogue I/O, digital mixing and routing,
signal processing and programmable DSPs.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
gplv2 only
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Armijn Hemel <armijn@tjaldur.nl>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.666840552@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see http www gnu org licenses gpl 2
0 html for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 2 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Enrico Weigelt <info@metux.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081205.243665028@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licenses
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 503 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Enrico Weigelt <info@metux.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this software is licensed under the terms of the gnu general public
license version 2 as published by the free software foundation and
may be copied distributed and modified under those terms
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 6 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190602204653.720704315@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The patch on this branch adds bindings for tohdmitx, including a header
to be used in DT bindings which needs to be shared with the arm-soc tree
in order to allow system DTs to be merged.
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Merge tag 'asoc-tohdmitx' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into HEAD
ASoC: tohdmitx bindings
The patch on this branch adds bindings for tohdmitx, including a header
to be used in DT bindings which needs to be shared with the arm-soc tree
in order to allow system DTs to be merged.
# gpg: Signature made Fri 14 Jun 2019 11:43:33 AM PDT
# gpg: using RSA key ADE668AA675718B59FE29FEA24D68B725D5487D0
# gpg: issuer "broonie@kernel.org"
# gpg: Good signature from "Mark Brown <broonie@sirena.org.uk>" [full]
# gpg: aka "Mark Brown <broonie@debian.org>" [full]
# gpg: aka "Mark Brown <broonie@kernel.org>" [full]
# gpg: aka "Mark Brown <broonie@tardis.ed.ac.uk>" [full]
# gpg: aka "Mark Brown <broonie@linaro.org>" [unknown]
# gpg: aka "Mark Brown <Mark.Brown@linaro.org>" [unknown]
* tag 'asoc-tohdmitx' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound:
ASoC: meson: add tohdmitx DT bindings
Add the bindings and the related documentation for the audio hdmitx
control glue of the Amlogic g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add binding for the QMP based side-channel communication mechanism to
the AOSS, which is used to control resources not exposed through the
RPMh interface.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add clock ids used by the temperature sensors of the G12A Socs
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit message]
The audio controllers on Meson8, Meson8b and Meson8m2 use similar
(potentially the same) audio clocks as GXBB, GXL and GXM. Add the
CLKID_CTS_AMCLK, CLKID_CTS_MCLK_I958 and CLKID_CTS_I958 clock IDs so
they can be used for the audio controllers.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
