The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.
Move them to the gcc clock group.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org
Fixes: e7fb524cfc ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Based on 1 normalized pattern(s):
this software is licensed under the terms of the gnu general public
license version 2 as published by the free software foundation and
may be copied distributed and modified under those terms this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 285 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PCIE and NSS has MISC reset register in which single register has
multiple reset bit. The patch adds the DT bindings for these MISC
resets.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the DT bindings for following IPQ8074 clocks
- General PLL’s, NSS UBI PLL and NSS Crypto PLL.
- 2 instances of PCIE, USB, SDCC.
- 2 NSS UBI core and common NSS clocks. NSS is network switching
system which accelerates the ethernet traffic. IPQ8074
NSS has two UBI cores. Some clocks are separate for each UBI core
and remaining NSS clocks are common.
- NSS ethernet port clocks. IPQ8074 has 6 ethernet ports and
each port uses different TX and RX clocks.
- Crypto engine clocks.
- General purpose clocks which comes over GPIO.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the compatible strings and the include file for ipq8074 gcc
clock controller.
Acked-by: Rob Herring <robh@kernel.org> (bindings)
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
