Commit Graph

1 Commits

Author SHA1 Message Date
Yoshihiro Shimoda
fa2d185f75 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V3U (R8A779A0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10 16:58:13 +02:00