forked from luck/tmp_suning_uos_patched
d36b49b910
The local apic timer calibration has two problem cases: 1. The calibration is based on readout of the PIT/HPET timer to detect the wrap of the periodic tick. It happens that a box gets stuck in the calibration loop due to a PIT with a broken readout function. 2. CoreDuo boxen show a sporadic PIT runs too slow defect, which results in a wrong lapic calibration. The PIT goes back to normal operation once the lapic timer is switched to periodic mode. Both are existing and unfixed problems in the current upstream kernel and prevent certain laptops and other systems from booting Linux. Rework the code to address both problems: - Make the calibration interrupt driven. This removes the wait_timer_tick magic hackery from lapic.c and time_hpet.c. The clockevents framework allows easy substitution of the global tick event handler for the calibration. This is more accurate than monitoring jiffies. At this point of the boot process, nothing disturbes the interrupt delivery, so the results are very accurate. - Verify the calibration against the PM timer, when available by using the early access function. When the measured calibration period is outside of an one percent window, then the lapic timer calibration is adjusted to the pm timer result. - Verify the calibration by running the lapic timer with the calibration handler. Disable lapic timer in case of deviation. This also removes the "synchronization" of the local apic timer to the global tick. This synchronization never worked, as there is no way to synchronize PIT(HPET) and local APIC timer. The synchronization by waiting for the tick just alignes the local APIC timer for the first events, but later the events drift away due to the different clocks. Removing the "sync" is just randomizing the asynchronous behaviour at setup time. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Zachary Amsden <zach@vmware.com> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Rohit Seth <rohitseth@google.com> Cc: Andi Kleen <ak@suse.de> Cc: john stultz <johnstul@us.ibm.com> Cc: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/pm.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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extern int apic_verbosity;
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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extern void generic_apic_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define apic_write native_apic_write
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#define apic_write_atomic native_apic_write_atomic
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#define apic_read native_apic_read
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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#endif
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static __inline fastcall void native_apic_write(unsigned long reg,
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unsigned long v)
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{
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*((volatile unsigned long *)(APIC_BASE+reg)) = v;
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}
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static __inline fastcall void native_apic_write_atomic(unsigned long reg,
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unsigned long v)
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{
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xchg((volatile unsigned long *)(APIC_BASE+reg), v);
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}
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static __inline fastcall unsigned long native_apic_read(unsigned long reg)
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{
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return *((volatile unsigned long *)(APIC_BASE+reg));
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}
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static __inline__ void apic_wait_icr_idle(void)
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{
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while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
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cpu_relax();
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}
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int get_physical_broadcast(void);
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x)
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# define apic_write_around(x,y) apic_write((x),(y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x,y) apic_write_atomic((x),(y))
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC (void);
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extern void disconnect_bsp_APIC (int virt_wire_setup);
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extern void disable_local_APIC (void);
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extern void lapic_shutdown (void);
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extern int verify_local_APIC (void);
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extern void cache_APIC_registers (void);
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extern void sync_Arb_IDs (void);
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extern void init_bsp_APIC (void);
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extern void setup_local_APIC (void);
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extern void init_apic_mappings (void);
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extern void smp_local_timer_interrupt (void);
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extern void setup_boot_APIC_clock (void);
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extern void setup_secondary_APIC_clock (void);
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extern int APIC_init_uniprocessor (void);
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extern void enable_NMI_through_LVT0 (void * dummy);
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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extern int timer_over_8254;
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_APIC_H */
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