forked from luck/tmp_suning_uos_patched
8118d12494
ICIP2 is not examined during IRQ entrance, this patch add the checking if the processor is PXA27x or later, with CoreG bits in CPUID (Core Generation) > 1 Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
58 lines
1.3 KiB
ArmAsm
58 lines
1.3 KiB
ArmAsm
/*
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* include/asm-arm/arch-pxa/entry-macro.S
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*
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* Low-level IRQ helper macros for PXA-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
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mov \tmp, \tmp, lsr #13
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and \tmp, \tmp, #0x7 @ Core G
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cmp \tmp, #1
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bhi 1004f
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mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
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add \base, \base, #0x00d00000
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ldr \irqstat, [\base, #0] @ ICIP
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ldr \irqnr, [\base, #4] @ ICMR
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b 1002f
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1004:
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mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
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mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
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ands \irqstat, \irqstat, \irqnr
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beq 1003f
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rsb \irqstat, \irqnr, #0
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and \irqstat, \irqstat, \irqnr
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #31
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add \irqnr, \irqnr, #32
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b 1001f
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1003:
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mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
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mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
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1002:
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ands \irqnr, \irqstat, \irqnr
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beq 1001f
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rsb \irqstat, \irqnr, #0
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and \irqstat, \irqstat, \irqnr
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #31
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1001:
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.endm
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