kernel_optimize_test/arch/arm/mach-tegra
Russell King 02b4e2756e ARM: v7 setup function should invalidate L1 cache
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU.  This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state.  Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-01 11:30:26 +01:00
..
board-paz00.c This is the bulk of GPIO changes for the v3.17 development 2014-08-08 18:00:35 -07:00
board.h ARM: tegra: Convert PMC to a driver 2014-07-17 14:58:43 +02:00
common.h Revert "ARM: tegra: add cpu_disable for hotplug" 2013-07-19 10:00:37 -06:00
cpuidle-tegra20.c Power management and ACPI updates for v4.1-rc1 2015-04-14 20:21:54 -07:00
cpuidle-tegra30.c Power management and ACPI updates for v4.1-rc1 2015-04-14 20:21:54 -07:00
cpuidle-tegra114.c ARM: Tegra: Use explicit broadcast oneshot control function 2015-04-03 08:44:35 +02:00
cpuidle.c ARM: tegra: Use a function to get the chip ID 2014-07-17 13:36:41 +02:00
cpuidle.h ARM: tegra: disable LP2 cpuidle state if PCIe is enabled 2013-08-13 12:07:56 -06:00
flowctrl.c ARM: tegra: Initialize flow controller from DT 2014-08-26 11:43:55 -06:00
flowctrl.h ARM: tegra: Initialize flow controller from DT 2014-08-26 11:43:55 -06:00
hotplug.c ARM: tegra: Setup CPU hotplug in a pure initcall 2014-07-17 14:58:41 +02:00
io.c ARM: tegra: Sort includes alphabetically 2014-07-17 13:29:57 +02:00
iomap.h ARM: tegra: remove old LIC support 2015-03-15 00:40:52 +00:00
irammap.h ARM: tegra: move resume vector define to irammap.h 2013-09-17 13:44:22 -06:00
irq.c ARM: tegra: remove old LIC support 2015-03-15 00:40:52 +00:00
irq.h ARM: tegra: remove old LIC support 2015-03-15 00:40:52 +00:00
Kconfig clocksource: Build Tegra timer on 32-bit ARM only 2015-01-09 14:45:43 +01:00
Makefile ARM: v7 setup function should invalidate L1 cache 2015-06-01 11:30:26 +01:00
platsmp.c ARM: tegra: Convert PMC to a driver 2014-07-17 14:58:43 +02:00
pm-tegra20.c ARM: tegra: Sort includes alphabetically 2014-07-17 13:29:57 +02:00
pm-tegra30.c ARM: tegra: Sort includes alphabetically 2014-07-17 13:29:57 +02:00
pm.c ARM: tegra: Convert PMC to a driver 2014-07-17 14:58:43 +02:00
pm.h ARM: tegra: Convert PMC to a driver 2014-07-17 14:58:43 +02:00
reset-handler.S ARM: tegra: Re-add removed SoC id macro to tegra_resume() 2014-11-17 11:43:21 +01:00
reset.c ARM: v7 setup function should invalidate L1 cache 2015-06-01 11:30:26 +01:00
reset.h ARM: v7 setup function should invalidate L1 cache 2015-06-01 11:30:26 +01:00
sleep-tegra20.S ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ 2014-07-18 12:29:04 +01:00
sleep-tegra30.S ARM: SoC cleanups for 3.17 2014-08-08 11:00:26 -07:00
sleep.h ARM: tegra: Setup CPU hotplug in a pure initcall 2014-07-17 14:58:41 +02:00
sleep.S ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ 2014-07-18 12:29:04 +01:00
tegra.c ARM: tegra: skip gic_arch_extn setup if DT has a LIC node 2015-03-15 00:40:39 +00:00