forked from luck/tmp_suning_uos_patched
02ca5083f6
Move SHDMA_SLAVE_NUMBER from asm/dmaengine.h to shdma.h. Set it to 256 to support a wide range of processors. The amount of memory consumed by this change is limited to 256 bits. While at it, rename to SH_DMA_SLAVE_NUMBER to match with the rest of the file. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
93 lines
2.0 KiB
C
93 lines
2.0 KiB
C
/*
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* Header for the new SH dmaengine driver
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_DMAENGINE_H
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#define ASM_DMAENGINE_H
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#include <linux/dmaengine.h>
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#include <linux/list.h>
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#include <asm/dma-register.h>
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#define SH_DMAC_MAX_CHANNELS 6
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enum {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_SCIF5_TX,
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SHDMA_SLAVE_SCIF5_RX,
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SHDMA_SLAVE_SIUA_TX,
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_RX,
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};
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struct sh_dmae_slave_config {
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unsigned int slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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};
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struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int dmars_bit;
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};
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struct sh_dmae_pdata {
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struct sh_dmae_slave_config *slave;
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int slave_num;
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struct sh_dmae_channel *channel;
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int channel_num;
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unsigned int ts_low_shift;
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unsigned int ts_low_mask;
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unsigned int ts_high_shift;
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unsigned int ts_high_mask;
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unsigned int *ts_shift;
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int ts_shift_num;
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u16 dmaor_init;
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};
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struct device;
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/* Used by slave DMA clients to request DMA to/from a specific peripheral */
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struct sh_dmae_slave {
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unsigned int slave_id; /* Set by the platform */
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struct device *dma_dev; /* Set by the platform */
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struct sh_dmae_slave_config *config; /* Set by the driver */
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};
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struct sh_dmae_regs {
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u32 sar; /* SAR / source address */
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u32 dar; /* DAR / destination address */
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u32 tcr; /* TCR / transfer count */
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};
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struct sh_desc {
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struct sh_dmae_regs hw;
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struct list_head node;
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struct dma_async_tx_descriptor async_tx;
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enum dma_data_direction direction;
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dma_cookie_t cookie;
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size_t partial;
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int chunks;
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int mark;
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};
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#endif
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