forked from luck/tmp_suning_uos_patched
1f83b8f148
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
/*
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* File: arch/blackfin/mach-bf533/ints-priority.c
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* Based on:
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* Author: Michael Hennerich
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*
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* Created: ?
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* Description: Set up the interrupt priorities
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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void program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) |
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((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) |
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((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) |
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((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) |
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((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) |
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((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) |
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((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) |
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((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS));
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bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) |
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((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) |
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((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) |
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((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) |
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((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) |
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((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) |
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((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) |
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((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS));
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bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) |
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((CONFIG_TIMER1 - 7) << TIMER1_POS) |
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((CONFIG_TIMER2 - 7) << TIMER2_POS) |
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((CONFIG_PFA - 7) << PFA_POS) |
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((CONFIG_PFB - 7) << PFB_POS) |
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((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) |
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((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) |
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((CONFIG_WDTIMER - 7) << WDTIMER_POS));
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SSYNC();
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}
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