forked from luck/tmp_suning_uos_patched
6210230725
BenH's commit a741e67969 in powerpc.git,
although (AFAICT) only intended to affect ppc64, also has side-effects
which break 44x. I think 40x, 8xx and Freescale Book E are also
affected, though I haven't tested them.
The problem lies in unconditionally removing flush_tlb_pending() from
the versions of flush_tlb_mm(), flush_tlb_range() and
flush_tlb_kernel_range() used on ppc64 - which are also used the
embedded platforms mentioned above.
The patch below cleans up the convoluted #ifdef logic in tlbflush.h,
in the process restoring the necessary flushes for the software TLB
platforms. There are three sets of definitions for the flushing
hooks: the software TLB versions (revised to avoid using names which
appear to related to TLB batching), the 32-bit hash based versions
(external functions) amd the 64-bit hash based versions (which
implement batching).
It also moves the declaration of update_mmu_cache() to always be in
tlbflush.h (previously it was in tlbflush.h except for PPC64, where it
was in pgtable.h).
Booted on Ebony (440GP) and compiled for 64-bit and 32-bit
multiplatform.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
183 lines
4.8 KiB
C
183 lines
4.8 KiB
C
#ifndef _ASM_POWERPC_TLBFLUSH_H
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#define _ASM_POWERPC_TLBFLUSH_H
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/*
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* TLB flushing:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifdef __KERNEL__
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struct mm_struct;
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struct vm_area_struct;
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#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
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/*
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* TLB flushing for software loaded TLB chips
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*
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* TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
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* flush_tlb_kernel_range are best implemented as tlbia vs
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* specific tlbie's
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*/
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extern void _tlbie(unsigned long address);
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#if defined(CONFIG_40x) || defined(CONFIG_8xx)
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#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
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#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
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extern void _tlbia(void);
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#endif
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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_tlbia();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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_tlbie(vmaddr);
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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_tlbie(vmaddr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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_tlbia();
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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_tlbia();
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}
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#elif defined(CONFIG_PPC32)
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/*
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* TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
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*/
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extern void _tlbie(unsigned long address);
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extern void _tlbia(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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#else
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/*
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* TLB flushing for 64-bit has-MMU CPUs
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*/
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#include <linux/percpu.h>
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#include <asm/page.h>
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#define PPC64_TLB_BATCH_NR 192
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struct ppc64_tlb_batch {
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int active;
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unsigned long index;
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struct mm_struct *mm;
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real_pte_t pte[PPC64_TLB_BATCH_NR];
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unsigned long vaddr[PPC64_TLB_BATCH_NR];
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unsigned int psize;
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};
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DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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static inline void arch_enter_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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batch->active = 1;
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}
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static inline void arch_leave_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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if (batch->index)
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__flush_tlb_pending(batch);
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batch->active = 0;
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}
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#define arch_flush_lazy_mmu_mode() do {} while (0)
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extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
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int local);
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extern void flush_hash_range(unsigned long number, int local);
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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}
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#endif
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/*
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* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
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* We use it to ensure coherency between the i-cache and d-cache
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* for the page which has just been mapped in.
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* On machines which use an MMU hash table, we use this to put a
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* corresponding HPTE into the hash table ahead of time, instead of
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* waiting for the inevitable extra hash-table miss exception.
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*/
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extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
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/*
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* This is called in munmap when we have freed up some page-table
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* pages. We don't need to do anything here, there's nothing special
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* about our page-table pages. -- paulus
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*/
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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}
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#endif /*__KERNEL__ */
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#endif /* _ASM_POWERPC_TLBFLUSH_H */
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