forked from luck/tmp_suning_uos_patched
d203a7eca8
Rewrite of the Indycam / VINO video v4l2 drivers for the SGI Indy. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Mikael Nousiainen <tmnousia@cc.hut.fi> Cc: <video4linux-list@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
140 lines
4.2 KiB
C
140 lines
4.2 KiB
C
/*
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* saa7191.h - Philips SAA7191 video decoder driver
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*
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* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
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* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _SAA7191_H_
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#define _SAA7191_H_
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/* Philips SAA7191 DMSD I2C bus address */
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#define SAA7191_ADDR 0x8a
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/* Register subaddresses. */
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#define SAA7191_REG_IDEL 0x00
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#define SAA7191_REG_HSYB 0x01
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#define SAA7191_REG_HSYS 0x02
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#define SAA7191_REG_HCLB 0x03
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#define SAA7191_REG_HCLS 0x04
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#define SAA7191_REG_HPHI 0x05
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#define SAA7191_REG_LUMA 0x06
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#define SAA7191_REG_HUEC 0x07
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#define SAA7191_REG_CKTQ 0x08
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#define SAA7191_REG_CKTS 0x09
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#define SAA7191_REG_PLSE 0x0a
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#define SAA7191_REG_SESE 0x0b
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#define SAA7191_REG_GAIN 0x0c
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#define SAA7191_REG_STDC 0x0d
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#define SAA7191_REG_IOCK 0x0e
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#define SAA7191_REG_CTL3 0x0f
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#define SAA7191_REG_CTL4 0x10
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#define SAA7191_REG_CHCV 0x11
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#define SAA7191_REG_HS6B 0x14
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#define SAA7191_REG_HS6S 0x15
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#define SAA7191_REG_HC6B 0x16
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#define SAA7191_REG_HC6S 0x17
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#define SAA7191_REG_HP6I 0x18
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#define SAA7191_REG_STATUS 0xff /* not really a subaddress */
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/* Status Register definitions */
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#define SAA7191_STATUS_CODE 0x01 /* color detected flag */
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#define SAA7191_STATUS_FIDT 0x20 /* format type NTSC/PAL */
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#define SAA7191_STATUS_HLCK 0x40 /* PLL unlocked/locked */
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#define SAA7191_STATUS_STTC 0x80 /* tv/vtr time constant */
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/* Luminance Control Register definitions */
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#define SAA7191_LUMA_BYPS 0x80
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/* Chroma Gain Control Settings Register definitions */
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/* 0=automatic colour-killer enabled, 1=forced colour on */
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#define SAA7191_GAIN_COLO 0x80
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/* Standard/Mode Control Register definitions */
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/* tv/vtr mode bit: 0=TV mode (slow time constant),
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* 1=VTR mode (fast time constant) */
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#define SAA7191_STDC_VTRC 0x80
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/* SECAM mode bit: 0=other standards, 1=SECAM */
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#define SAA7191_STDC_SECS 0x01
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/* the bit fields above must be or'd with this value */
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#define SAA7191_STDC_VALUE 0x0c
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/* I/O and Clock Control Register definitions */
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/* horizontal clock PLL: 0=PLL closed,
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* 1=PLL circuit open and horizontal freq fixed */
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#define SAA7191_IOCK_HPLL 0x80
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/* S-VHS bit (chrominance from CVBS or from chrominance input):
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* 0=controlled by BYPS-bit, 1=from chrominance input */
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#define SAA7191_IOCK_CHRS 0x04
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/* general purpose switch 2
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* VINO-specific: 0=used with CVBS, 1=used with S-Video */
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#define SAA7191_IOCK_GPSW2 0x02
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/* general purpose switch 1 */
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/* VINO-specific: 0=always, 1=not used!*/
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#define SAA7191_IOCK_GPSW1 0x01
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/* Miscellaneous Control #1 Register definitions */
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/* automatic field detection (50/60Hz standard) */
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#define SAA7191_CTL3_AUFD 0x80
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/* field select: (if AUFD=0)
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* 0=50Hz (625 lines), 1=60Hz (525 lines) */
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#define SAA7191_CTL3_FSEL 0x40
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/* the bit fields above must be or'd with this value */
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#define SAA7191_CTL3_VALUE 0x19
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/* Chrominance Gain Control Register definitions
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* (nominal value for UV CCIR level) */
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#define SAA7191_CHCV_NTSC 0x2c
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#define SAA7191_CHCV_PAL 0x59
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/* Driver interface definitions */
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#define SAA7191_INPUT_COMPOSITE 0
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#define SAA7191_INPUT_SVIDEO 1
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#define SAA7191_NORM_AUTO 0
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#define SAA7191_NORM_PAL 1
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#define SAA7191_NORM_NTSC 2
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#define SAA7191_NORM_SECAM 3
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#define SAA7191_VALUE_ENABLED 1
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#define SAA7191_VALUE_DISABLED 0
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#define SAA7191_VALUE_UNCHANGED -1
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struct saa7191_status {
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/* 0=no signal, 1=signal active*/
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int signal;
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/* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
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int ntsc;
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/* 0=no color detected, 1=color detected */
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int color;
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/* current SAA7191_INPUT_ */
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int input;
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/* current SAA7191_NORM_ */
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int norm;
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};
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#define SAA7191_HUE_MIN 0x00
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#define SAA7191_HUE_MAX 0xff
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#define SAA7191_HUE_DEFAULT 0x80
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#define SAA7191_VTRC_MIN 0x00
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#define SAA7191_VTRC_MAX 0x01
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#define SAA7191_VTRC_DEFAULT 0x00
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struct saa7191_control {
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int hue;
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int vtrc;
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};
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#define DECODER_SAA7191_GET_STATUS _IOR('d', 195, struct saa7191_status)
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#define DECODER_SAA7191_SET_NORM _IOW('d', 196, int)
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#define DECODER_SAA7191_GET_CONTROLS _IOR('d', 197, struct saa7191_control)
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#define DECODER_SAA7191_SET_CONTROLS _IOW('d', 198, struct saa7191_control)
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#endif
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