forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
445 lines
17 KiB
C
445 lines
17 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_SERIAL_H
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#define _ASM_SERIAL_H
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#include <linux/config.h>
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/*
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* This assumes you have a 1.8432 MHz clock for your UART.
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*
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* It'd be nice if someone built a serial card with a 24.576 MHz
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* clock, since the 16550A is capable of handling a top speed of 1.5
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* megabits/second; but this requires the faster clock.
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*/
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#define BASE_BAUD (1843200 / 16)
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/* Standard COM flags (except for COM4, because of the 8514 problem) */
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
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#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
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#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
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#endif
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define FOURPORT_FLAGS ASYNC_FOURPORT
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#define ACCENT_FLAGS 0
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#define BOCA_FLAGS 0
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#define HUB6_FLAGS 0
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#define RS_TABLE_SIZE 64
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#else
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#define RS_TABLE_SIZE
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#endif
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/*
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* The following define the access methods for the HUB6 card. All
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* access is through two ports for all 24 possible chips. The card is
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* selected through the high 2 bits, the port on that card with the
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* "middle" 3 bits, and the register on that port with the bottom
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* 3 bits.
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*
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* While the access port and interrupt is configurable, the default
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* port locations are 0x302 for the port control register, and 0x303
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* for the data read/write register. Normally, the interrupt is at irq3
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* but can be anything from 3 to 7 inclusive. Note that using 3 will
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* require disabling com2.
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*/
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#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
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#ifdef CONFIG_MACH_JAZZ
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#include <asm/jazz.h>
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#ifndef CONFIG_OLIVETTI_M700
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/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
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exactly which ones ... XXX */
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#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
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#else
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/* but the M700 isn't such a strange beast */
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#define JAZZ_BASE_BAUD BASE_BAUD
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#endif
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#define _JAZZ_SERIAL_INIT(int, base) \
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{ .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
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.io_type = SERIAL_IO_MEM }
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#define JAZZ_SERIAL_PORT_DEFNS \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
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#else
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#define JAZZ_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_COBALT
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#include <asm/cobalt/cobalt.h>
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#define COBALT_BASE_BAUD (18432000 / 16)
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#define COBALT_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
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#else
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#define COBALT_SERIAL_PORT_DEFNS
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#endif
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/*
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* Both Galileo boards have the same UART mappings.
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*/
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#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
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#include <asm/galileo-boards/ev96100.h>
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#include <asm/galileo-boards/ev96100int.h>
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#define EV96100_SERIAL_PORT_DEFNS \
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{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }, \
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{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM },
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#else
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#define EV96100_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_ITE8172
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#include <asm/it8712.h>
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#define ITE_SERIAL_PORT_DEFNS \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
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.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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{ .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
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.irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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/* Smart Card Reader 0 */ \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
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.irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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/* Smart Card Reader 1 */ \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
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.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
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#else
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#define ITE_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MIPS_IVR
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#define IVR_SERIAL_PORT_DEFNS \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
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.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
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/* Smart Card Reader 1 */ \
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{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
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.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
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#else
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#define IVR_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_TOSHIBA_JMR3927
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#include <asm/jmr3927/jmr3927.h>
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#define TXX927_SERIAL_PORT_DEFNS \
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{ .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
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.flags = UART0_FLAGS, .type = 1 }, \
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{ .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
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.flags = UART1_FLAGS, .type = 1 },
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#else
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#define TXX927_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_SERIAL_AU1X00
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_SOC_AU1000
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#define AU1000_SERIAL_PORT_DEFNS \
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{ .baud_base = 0, .port = UART0_ADDR, \
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.iomem_base = (unsigned char *)UART0_ADDR, \
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.irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART1_ADDR, \
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.iomem_base = (unsigned char *)UART1_ADDR, \
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.irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART2_ADDR, \
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.iomem_base = (unsigned char *)UART2_ADDR, \
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.irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART3_ADDR, \
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.iomem_base = (unsigned char *)UART3_ADDR, \
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.irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 },
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#endif
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#ifdef CONFIG_SOC_AU1500
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#define AU1000_SERIAL_PORT_DEFNS \
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{ .baud_base = 0, .port = UART0_ADDR, \
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.iomem_base = (unsigned char *)UART0_ADDR, \
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.irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART3_ADDR, \
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.iomem_base = (unsigned char *)UART3_ADDR, \
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.irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 },
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#endif
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#ifdef CONFIG_SOC_AU1100
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#define AU1000_SERIAL_PORT_DEFNS \
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{ .baud_base = 0, .port = UART0_ADDR, \
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.iomem_base = (unsigned char *)UART0_ADDR, \
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.irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART1_ADDR, \
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.iomem_base = (unsigned char *)UART1_ADDR, \
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.irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART3_ADDR, \
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.iomem_base = (unsigned char *)UART3_ADDR, \
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.irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 },
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#endif
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#ifdef CONFIG_SOC_AU1550
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#define AU1000_SERIAL_PORT_DEFNS \
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{ .baud_base = 0, .port = UART0_ADDR, \
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.iomem_base = (unsigned char *)UART0_ADDR, \
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.irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART1_ADDR, \
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.iomem_base = (unsigned char *)UART1_ADDR, \
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.irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART3_ADDR, \
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.iomem_base = (unsigned char *)UART3_ADDR, \
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.irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
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.iomem_reg_shift = 2 },
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#endif
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#ifdef CONFIG_SOC_AU1200
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#define AU1000_SERIAL_PORT_DEFNS \
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{ .baud_base = 0, .port = UART0_ADDR, \
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.iomem_base = (unsigned char *)UART0_ADDR, \
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.irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 }, \
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{ .baud_base = 0, .port = UART1_ADDR, \
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.iomem_base = (unsigned char *)UART1_ADDR, \
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.irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
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.iomem_reg_shift = 2 },
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#endif
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#else
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#define AU1000_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
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#define STD_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
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{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
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{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
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{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define EXTRA_SERIAL_PORT_DEFNS \
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{ 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
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{ 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
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{ 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
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{ 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
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{ 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
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{ 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
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{ 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
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{ 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
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{ 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
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{ 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
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{ 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
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{ 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
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{ 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
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{ 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
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{ 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
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{ 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
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{ 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
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{ 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
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{ 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
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{ 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
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{ 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
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{ 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
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{ 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
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{ 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
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{ 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
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{ 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
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{ 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
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{ 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
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#else /* CONFIG_SERIAL_MANY_PORTS */
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#define EXTRA_SERIAL_PORT_DEFNS
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#endif /* CONFIG_SERIAL_MANY_PORTS */
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#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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#define STD_SERIAL_PORT_DEFNS
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#define EXTRA_SERIAL_PORT_DEFNS
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#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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/* You can have up to four HUB6's in the system, but I've only
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* included two cards here for a total of twelve ports.
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*/
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#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
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#define HUB6_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
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{ 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
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#else
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#define HUB6_SERIAL_PORT_DFNS
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#endif
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#ifdef CONFIG_MOMENCO_JAGUAR_ATX
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define JAGUAR_ATX_UART_CLK 20000000
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#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
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#define JAGUAR_ATX_SERIAL1_IRQ 6
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#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
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#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
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{ baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \
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flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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iomem_base: (u8 *) base, iomem_reg_shift: 2, \
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io_type: SERIAL_IO_MEM }
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#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
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_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
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#else
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#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MOMENCO_OCELOT_3
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#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_3_SERIAL_IRQ 6
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#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
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#define _OCELOT_3_SERIAL_INIT(int, base) \
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{ baud_base: OCELOT_3_BASE_BAUD, irq: int, \
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flags: STD_COM_FLAGS, \
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iomem_base: (u8 *) base, iomem_reg_shift: 2, \
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io_type: SERIAL_IO_MEM }
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#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
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_OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
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#else
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#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MOMENCO_OCELOT
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define OCELOT_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_SERIAL1_IRQ 4
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#define OCELOT_SERIAL1_BASE 0xe0001020
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#define _OCELOT_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }
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#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
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_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
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#else
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#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
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#endif
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|
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#ifdef CONFIG_MOMENCO_OCELOT_G
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
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|
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#define OCELOT_G_SERIAL1_IRQ 4
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#if 0
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#define OCELOT_G_SERIAL1_BASE 0xe0001020
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#else
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#define OCELOT_G_SERIAL1_BASE 0xfd000020
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#endif
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|
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#define _OCELOT_G_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
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.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }
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#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
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_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
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#else
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#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
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#endif
|
|
|
|
#ifdef CONFIG_MOMENCO_OCELOT_C
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|
/* Ordinary NS16552 duart with a 20MHz crystal. */
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|
#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
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|
|
|
#define OCELOT_C_SERIAL1_IRQ 80
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#define OCELOT_C_SERIAL1_BASE 0xfd000020
|
|
|
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#define OCELOT_C_SERIAL2_IRQ 81
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|
#define OCELOT_C_SERIAL2_BASE 0xfd000000
|
|
|
|
#define _OCELOT_C_SERIAL_INIT(int, base) \
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|
{ .baud_base = OCELOT_C_BASE_BAUD, \
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|
.irq = (int), \
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|
.flags = STD_COM_FLAGS, \
|
|
.iomem_base = (u8 *) base, \
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|
.iomem_reg_shift = 2, \
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|
.io_type = SERIAL_IO_MEM \
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|
}
|
|
#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
|
|
_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
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|
_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
|
|
#else
|
|
#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
|
|
#endif
|
|
|
|
#ifdef CONFIG_DDB5477
|
|
#include <asm/ddb5xxx/ddb5477.h>
|
|
#define DDB5477_SERIAL_PORT_DEFNS \
|
|
{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
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|
.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
|
|
.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
|
|
{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
|
|
.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
|
|
.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
|
|
#else
|
|
#define DDB5477_SERIAL_PORT_DEFNS
|
|
#endif
|
|
|
|
#ifdef CONFIG_SGI_IP32
|
|
/*
|
|
* The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
|
|
* They are initialized in ip32_setup
|
|
*/
|
|
#define IP32_SERIAL_PORT_DEFNS \
|
|
{},{},
|
|
#else
|
|
#define IP32_SERIAL_PORT_DEFNS
|
|
#endif /* CONFIG_SGI_IP32 */
|
|
|
|
#define SERIAL_PORT_DFNS \
|
|
COBALT_SERIAL_PORT_DEFNS \
|
|
DDB5477_SERIAL_PORT_DEFNS \
|
|
EV96100_SERIAL_PORT_DEFNS \
|
|
EXTRA_SERIAL_PORT_DEFNS \
|
|
HUB6_SERIAL_PORT_DFNS \
|
|
IP32_SERIAL_PORT_DEFNS \
|
|
ITE_SERIAL_PORT_DEFNS \
|
|
IVR_SERIAL_PORT_DEFNS \
|
|
JAZZ_SERIAL_PORT_DEFNS \
|
|
STD_SERIAL_PORT_DEFNS \
|
|
MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
|
MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
|
|
MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
|
|
MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
|
|
TXX927_SERIAL_PORT_DEFNS \
|
|
AU1000_SERIAL_PORT_DEFNS
|
|
|
|
#endif /* _ASM_SERIAL_H */
|