forked from luck/tmp_suning_uos_patched
ec8f5d8f6f
The driver is separated by functional parts. The core part implements a platform driver probe and remove callbaks. The probe enables clocks, checks crypto version, initialize and request dma channels, create done tasklet and init crypto queue and finally register the algorithms into crypto core subsystem. - DMA and SG helper functions implement dmaengine and sg-list helper functions used by other parts of the crypto driver. - ablkcipher algorithms implementation of AES, DES and 3DES crypto API callbacks, the crypto register alg function, the async request handler and its dma done callback function. - SHA and HMAC transforms implementation and registration of ahash crypto type. It includes sha1, sha256, hmac(sha1) and hmac(sha256). - infrastructure to setup the crypto hw contains functions used to setup/prepare hardware registers for all algorithms supported by the crypto block. It also exports few helper functions needed by algorithms: - to check hardware status - to start crypto hardware - to translate data stream to big endian form Adds register addresses and bit/masks used by the driver as well. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CORE_H_
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#define _CORE_H_
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#include "dma.h"
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/**
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* struct qce_device - crypto engine device structure
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* @queue: crypto request queue
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* @lock: the lock protects queue and req
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* @done_tasklet: done tasklet object
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* @req: current active request
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* @result: result of current transform
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* @base: virtual IO base
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* @dev: pointer to device structure
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* @core: core device clock
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* @iface: interface clock
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* @bus: bus clock
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* @dma: pointer to dma data
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* @burst_size: the crypto burst size
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* @pipe_pair_id: which pipe pair id the device using
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* @async_req_enqueue: invoked by every algorithm to enqueue a request
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* @async_req_done: invoked by every algorithm to finish its request
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*/
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struct qce_device {
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struct crypto_queue queue;
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spinlock_t lock;
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struct tasklet_struct done_tasklet;
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struct crypto_async_request *req;
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int result;
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void __iomem *base;
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struct device *dev;
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struct clk *core, *iface, *bus;
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struct qce_dma_data dma;
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int burst_size;
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unsigned int pipe_pair_id;
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int (*async_req_enqueue)(struct qce_device *qce,
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struct crypto_async_request *req);
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void (*async_req_done)(struct qce_device *qce, int ret);
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};
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/**
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* struct qce_algo_ops - algorithm operations per crypto type
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* @type: should be CRYPTO_ALG_TYPE_XXX
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* @register_algs: invoked by core to register the algorithms
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* @unregister_algs: invoked by core to unregister the algorithms
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* @async_req_handle: invoked by core to handle enqueued request
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*/
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struct qce_algo_ops {
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u32 type;
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int (*register_algs)(struct qce_device *qce);
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void (*unregister_algs)(struct qce_device *qce);
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int (*async_req_handle)(struct crypto_async_request *async_req);
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};
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#endif /* _CORE_H_ */
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