forked from luck/tmp_suning_uos_patched
3149be50d3
SM502 has a programmable PLL which can provide the panel pixel clock instead of the 288MHz and 336MHz PLLs. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Ville Syrjala <syrjala@sci.fi> Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
387 lines
12 KiB
C
387 lines
12 KiB
C
/* sm501-regs.h
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*
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* Copyright 2006 Simtec Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Silicon Motion SM501 register definitions
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*/
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/* System Configuration area */
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/* System config base */
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#define SM501_SYS_CONFIG (0x000000)
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/* config 1 */
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#define SM501_SYSTEM_CONTROL (0x000000)
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#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
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#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
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#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
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#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
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#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
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#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
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#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
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/* miscellaneous control */
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#define SM501_MISC_CONTROL (0x000004)
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#define SM501_MISC_BUS_SH (0x0)
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#define SM501_MISC_BUS_PCI (0x1)
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#define SM501_MISC_BUS_XSCALE (0x2)
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#define SM501_MISC_BUS_NEC (0x6)
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#define SM501_MISC_BUS_MASK (0x7)
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#define SM501_MISC_VR_62MB (1<<3)
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#define SM501_MISC_CDR_RESET (1<<7)
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#define SM501_MISC_USB_LB (1<<8)
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#define SM501_MISC_USB_SLAVE (1<<9)
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#define SM501_MISC_BL_1 (1<<10)
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#define SM501_MISC_MC (1<<11)
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#define SM501_MISC_DAC_POWER (1<<12)
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#define SM501_MISC_IRQ_INVERT (1<<16)
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#define SM501_MISC_SH (1<<17)
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#define SM501_MISC_HOLD_EMPTY (0<<18)
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#define SM501_MISC_HOLD_8 (1<<18)
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#define SM501_MISC_HOLD_16 (2<<18)
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#define SM501_MISC_HOLD_24 (3<<18)
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#define SM501_MISC_HOLD_32 (4<<18)
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#define SM501_MISC_HOLD_MASK (7<<18)
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#define SM501_MISC_FREQ_12 (1<<24)
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#define SM501_MISC_PNL_24BIT (1<<25)
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#define SM501_MISC_8051_LE (1<<26)
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#define SM501_GPIO31_0_CONTROL (0x000008)
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#define SM501_GPIO63_32_CONTROL (0x00000C)
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#define SM501_DRAM_CONTROL (0x000010)
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/* command list */
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#define SM501_ARBTRTN_CONTROL (0x000014)
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/* command list */
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#define SM501_COMMAND_LIST_STATUS (0x000024)
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/* interrupt debug */
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#define SM501_RAW_IRQ_STATUS (0x000028)
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#define SM501_RAW_IRQ_CLEAR (0x000028)
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#define SM501_IRQ_STATUS (0x00002C)
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#define SM501_IRQ_MASK (0x000030)
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#define SM501_DEBUG_CONTROL (0x000034)
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/* power management */
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#define SM501_POWERMODE_P2X_SRC (1<<29)
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#define SM501_POWERMODE_V2X_SRC (1<<20)
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#define SM501_POWERMODE_M_SRC (1<<12)
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#define SM501_POWERMODE_M1_SRC (1<<4)
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#define SM501_CURRENT_GATE (0x000038)
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#define SM501_CURRENT_CLOCK (0x00003C)
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#define SM501_POWER_MODE_0_GATE (0x000040)
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#define SM501_POWER_MODE_0_CLOCK (0x000044)
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#define SM501_POWER_MODE_1_GATE (0x000048)
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#define SM501_POWER_MODE_1_CLOCK (0x00004C)
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#define SM501_SLEEP_MODE_GATE (0x000050)
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#define SM501_POWER_MODE_CONTROL (0x000054)
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/* power gates for units within the 501 */
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#define SM501_GATE_HOST (0)
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#define SM501_GATE_MEMORY (1)
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#define SM501_GATE_DISPLAY (2)
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#define SM501_GATE_2D_ENGINE (3)
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#define SM501_GATE_CSC (4)
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#define SM501_GATE_ZVPORT (5)
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#define SM501_GATE_GPIO (6)
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#define SM501_GATE_UART0 (7)
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#define SM501_GATE_UART1 (8)
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#define SM501_GATE_SSP (10)
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#define SM501_GATE_USB_HOST (11)
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#define SM501_GATE_USB_GADGET (12)
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#define SM501_GATE_UCONTROLLER (17)
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#define SM501_GATE_AC97 (18)
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/* panel clock */
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#define SM501_CLOCK_P2XCLK (24)
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/* crt clock */
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#define SM501_CLOCK_V2XCLK (16)
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/* main clock */
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#define SM501_CLOCK_MCLK (8)
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/* SDRAM controller clock */
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#define SM501_CLOCK_M1XCLK (0)
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/* config 2 */
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#define SM501_PCI_MASTER_BASE (0x000058)
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#define SM501_ENDIAN_CONTROL (0x00005C)
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#define SM501_DEVICEID (0x000060)
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/* 0x050100A0 */
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#define SM501_DEVICEID_SM501 (0x05010000)
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#define SM501_DEVICEID_IDMASK (0xffff0000)
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#define SM501_DEVICEID_REVMASK (0x000000ff)
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#define SM501_PLLCLOCK_COUNT (0x000064)
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#define SM501_MISC_TIMING (0x000068)
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#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
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#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
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/* GPIO base */
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#define SM501_GPIO (0x010000)
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#define SM501_GPIO_DATA_LOW (0x00)
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#define SM501_GPIO_DATA_HIGH (0x04)
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#define SM501_GPIO_DDR_LOW (0x08)
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#define SM501_GPIO_DDR_HIGH (0x0C)
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#define SM501_GPIO_IRQ_SETUP (0x10)
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#define SM501_GPIO_IRQ_STATUS (0x14)
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#define SM501_GPIO_IRQ_RESET (0x14)
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/* I2C controller base */
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#define SM501_I2C (0x010040)
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#define SM501_I2C_BYTE_COUNT (0x00)
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#define SM501_I2C_CONTROL (0x01)
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#define SM501_I2C_STATUS (0x02)
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#define SM501_I2C_RESET (0x02)
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#define SM501_I2C_SLAVE_ADDRESS (0x03)
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#define SM501_I2C_DATA (0x04)
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/* SSP base */
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#define SM501_SSP (0x020000)
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/* Uart 0 base */
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#define SM501_UART0 (0x030000)
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/* Uart 1 base */
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#define SM501_UART1 (0x030020)
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/* USB host port base */
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#define SM501_USB_HOST (0x040000)
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/* USB slave/gadget base */
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#define SM501_USB_GADGET (0x060000)
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/* USB slave/gadget data port base */
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#define SM501_USB_GADGET_DATA (0x070000)
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/* Display controller/video engine base */
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#define SM501_DC (0x080000)
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/* common defines for the SM501 address registers */
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#define SM501_ADDR_FLIP (1<<31)
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#define SM501_ADDR_EXT (1<<27)
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#define SM501_ADDR_CS1 (1<<26)
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#define SM501_ADDR_MASK (0x3f << 26)
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#define SM501_FIFO_MASK (0x3 << 16)
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#define SM501_FIFO_1 (0x0 << 16)
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#define SM501_FIFO_3 (0x1 << 16)
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#define SM501_FIFO_7 (0x2 << 16)
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#define SM501_FIFO_11 (0x3 << 16)
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/* common registers for panel and the crt */
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#define SM501_OFF_DC_H_TOT (0x000)
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#define SM501_OFF_DC_V_TOT (0x008)
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#define SM501_OFF_DC_H_SYNC (0x004)
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#define SM501_OFF_DC_V_SYNC (0x00C)
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#define SM501_DC_PANEL_CONTROL (0x000)
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#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
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#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
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#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
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#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
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#define SM501_DC_PANEL_CONTROL_DP (1<<23)
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#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
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#define SM501_DC_PANEL_CONTROL_DE (1<<20)
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#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
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#define SM501_DC_PANEL_CONTROL_CP (1<<14)
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#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
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#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
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#define SM501_DC_PANEL_CONTROL_CK (1<<9)
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#define SM501_DC_PANEL_CONTROL_TE (1<<8)
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#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
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#define SM501_DC_PANEL_CONTROL_VP (1<<6)
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#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
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#define SM501_DC_PANEL_CONTROL_HP (1<<4)
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#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
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#define SM501_DC_PANEL_CONTROL_EN (1<<2)
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#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
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#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
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#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
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#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
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#define SM501_DC_PANEL_COLOR_KEY (0x008)
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#define SM501_DC_PANEL_FB_ADDR (0x00C)
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#define SM501_DC_PANEL_FB_OFFSET (0x010)
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#define SM501_DC_PANEL_FB_WIDTH (0x014)
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#define SM501_DC_PANEL_FB_HEIGHT (0x018)
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#define SM501_DC_PANEL_TL_LOC (0x01C)
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#define SM501_DC_PANEL_BR_LOC (0x020)
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#define SM501_DC_PANEL_H_TOT (0x024)
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#define SM501_DC_PANEL_H_SYNC (0x028)
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#define SM501_DC_PANEL_V_TOT (0x02C)
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#define SM501_DC_PANEL_V_SYNC (0x030)
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#define SM501_DC_PANEL_CUR_LINE (0x034)
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#define SM501_DC_VIDEO_CONTROL (0x040)
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#define SM501_DC_VIDEO_FB0_ADDR (0x044)
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#define SM501_DC_VIDEO_FB_WIDTH (0x048)
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#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
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#define SM501_DC_VIDEO_TL_LOC (0x050)
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#define SM501_DC_VIDEO_BR_LOC (0x054)
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#define SM501_DC_VIDEO_SCALE (0x058)
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#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
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#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
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#define SM501_DC_VIDEO_FB1_ADDR (0x064)
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#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
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#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
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#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
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#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
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#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
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#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
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#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
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#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
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#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
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#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
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#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
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#define SM501_DC_PANEL_HWC_BASE (0x0F0)
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#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
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#define SM501_DC_PANEL_HWC_LOC (0x0F4)
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#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
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#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
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#define SM501_HWC_EN (1<<31)
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#define SM501_OFF_HWC_ADDR (0x00)
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#define SM501_OFF_HWC_LOC (0x04)
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#define SM501_OFF_HWC_COLOR_1_2 (0x08)
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#define SM501_OFF_HWC_COLOR_3 (0x0C)
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#define SM501_DC_ALPHA_CONTROL (0x100)
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#define SM501_DC_ALPHA_FB_ADDR (0x104)
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#define SM501_DC_ALPHA_FB_OFFSET (0x108)
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#define SM501_DC_ALPHA_TL_LOC (0x10C)
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#define SM501_DC_ALPHA_BR_LOC (0x110)
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#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
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#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
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#define SM501_DC_CRT_CONTROL (0x200)
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#define SM501_DC_CRT_CONTROL_TVP (1<<15)
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#define SM501_DC_CRT_CONTROL_CP (1<<14)
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#define SM501_DC_CRT_CONTROL_VSP (1<<13)
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#define SM501_DC_CRT_CONTROL_HSP (1<<12)
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#define SM501_DC_CRT_CONTROL_VS (1<<11)
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#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
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#define SM501_DC_CRT_CONTROL_SEL (1<<9)
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#define SM501_DC_CRT_CONTROL_TE (1<<8)
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#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
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#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
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#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
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#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
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#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
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#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
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#define SM501_DC_CRT_FB_ADDR (0x204)
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#define SM501_DC_CRT_FB_OFFSET (0x208)
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#define SM501_DC_CRT_H_TOT (0x20C)
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#define SM501_DC_CRT_H_SYNC (0x210)
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#define SM501_DC_CRT_V_TOT (0x214)
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#define SM501_DC_CRT_V_SYNC (0x218)
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#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
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#define SM501_DC_CRT_CUR_LINE (0x220)
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#define SM501_DC_CRT_MONITOR_DETECT (0x224)
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#define SM501_DC_CRT_HWC_BASE (0x230)
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#define SM501_DC_CRT_HWC_ADDR (0x230)
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#define SM501_DC_CRT_HWC_LOC (0x234)
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#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
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#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
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#define SM501_DC_PANEL_PALETTE (0x400)
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#define SM501_DC_VIDEO_PALETTE (0x800)
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#define SM501_DC_CRT_PALETTE (0xC00)
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/* Zoom Video port base */
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#define SM501_ZVPORT (0x090000)
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/* AC97/I2S base */
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#define SM501_AC97 (0x0A0000)
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/* 8051 micro controller base */
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#define SM501_UCONTROLLER (0x0B0000)
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/* 8051 micro controller SRAM base */
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#define SM501_UCONTROLLER_SRAM (0x0C0000)
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/* DMA base */
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#define SM501_DMA (0x0D0000)
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/* 2d engine base */
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#define SM501_2D_ENGINE (0x100000)
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#define SM501_2D_SOURCE (0x00)
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#define SM501_2D_DESTINATION (0x04)
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#define SM501_2D_DIMENSION (0x08)
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#define SM501_2D_CONTROL (0x0C)
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#define SM501_2D_PITCH (0x10)
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#define SM501_2D_FOREGROUND (0x14)
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#define SM501_2D_BACKGROUND (0x18)
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#define SM501_2D_STRETCH (0x1C)
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#define SM501_2D_COLOR_COMPARE (0x20)
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#define SM501_2D_COLOR_COMPARE_MASK (0x24)
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#define SM501_2D_MASK (0x28)
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#define SM501_2D_CLIP_TL (0x2C)
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#define SM501_2D_CLIP_BR (0x30)
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#define SM501_2D_MONO_PATTERN_LOW (0x34)
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#define SM501_2D_MONO_PATTERN_HIGH (0x38)
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#define SM501_2D_WINDOW_WIDTH (0x3C)
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#define SM501_2D_SOURCE_BASE (0x40)
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#define SM501_2D_DESTINATION_BASE (0x44)
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#define SM501_2D_ALPHA (0x48)
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#define SM501_2D_WRAP (0x4C)
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#define SM501_2D_STATUS (0x50)
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#define SM501_CSC_Y_SOURCE_BASE (0xC8)
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#define SM501_CSC_CONSTANTS (0xCC)
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#define SM501_CSC_Y_SOURCE_X (0xD0)
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#define SM501_CSC_Y_SOURCE_Y (0xD4)
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#define SM501_CSC_U_SOURCE_BASE (0xD8)
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#define SM501_CSC_V_SOURCE_BASE (0xDC)
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#define SM501_CSC_SOURCE_DIMENSION (0xE0)
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#define SM501_CSC_SOURCE_PITCH (0xE4)
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#define SM501_CSC_DESTINATION (0xE8)
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#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
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#define SM501_CSC_DESTINATION_PITCH (0xF0)
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#define SM501_CSC_SCALE_FACTOR (0xF4)
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#define SM501_CSC_DESTINATION_BASE (0xF8)
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#define SM501_CSC_CONTROL (0xFC)
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/* 2d engine data port base */
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#define SM501_2D_ENGINE_DATA (0x110000)
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