forked from luck/tmp_suning_uos_patched
d8a944582d
The OMAP2 clock code currently #includes a large .h file full of static
data structures. Instead, define the data in a .c file.
Russell King <linux@arm.linux.org.uk> proposed this new arrangement:
http://marc.info/?l=linux-omap&m=125967425908895&w=2
This patch also deals with most of the flagrant checkpatch violations.
While here, separate the prcm_config data structures out into their own
files, opp2xxx.h and opp24{2,3}0_data.c, and only build in the OPP tables
for the target device. This should save some memory. In the long run,
these prcm_config tables should be replaced with OPP code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Nishanth Menon <nm@ti.com>
79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
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#define __ARCH_ARM_MACH_OMAP2_SDRC_H
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/*
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* OMAP2 SDRC register definitions
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Copyright (C) 2007 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <plat/sdrc.h>
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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extern void __iomem *omap2_sdrc_base;
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extern void __iomem *omap2_sms_base;
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#define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
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#define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
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/* SDRC global register get/set */
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static inline void sdrc_write_reg(u32 val, u16 reg)
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{
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__raw_writel(val, OMAP_SDRC_REGADDR(reg));
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}
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static inline u32 sdrc_read_reg(u16 reg)
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{
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return __raw_readl(OMAP_SDRC_REGADDR(reg));
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}
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/* SMS global register get/set */
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static inline void sms_write_reg(u32 val, u16 reg)
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{
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__raw_writel(val, OMAP_SMS_REGADDR(reg));
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}
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static inline u32 sms_read_reg(u16 reg)
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{
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return __raw_readl(OMAP_SMS_REGADDR(reg));
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}
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#else
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#define OMAP242X_SDRC_REGADDR(reg) \
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OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
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#define OMAP243X_SDRC_REGADDR(reg) \
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OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
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#define OMAP34XX_SDRC_REGADDR(reg) \
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OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
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#endif /* __ASSEMBLER__ */
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/* Minimum frequency that the SDRC DLL can lock at */
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#define MIN_SDRC_DLL_LOCK_FREQ 83000000
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/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
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#define SDRC_MPURATE_SCALE 8
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/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
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#define SDRC_MPURATE_BASE_SHIFT 9
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/*
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* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
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* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
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*/
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#define SDRC_MPURATE_LOOPS 96
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#endif
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