Maciej W. Rozycki 0fabe1021f MIPS: DECstation I/O ASIC DMA interrupt classes ... This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4 [MIPS: DEC: Convert to new irq_chip functions] and 5359b938c0 [MIPS: DECstation I/O ASIC DMA interrupt handling fix] and implements automatic handling of the two classes of DMA interrupts the I/O ASIC implements, informational and errors. Informational DMA interrupts do not stop the transfer and use the `handle_edge_irq' handler that clears the request right away so that another request may be recorded while the previous is being handled. DMA error interrupts stop the transfer and require a corrective action before DMA can be reenabled. Therefore they use the `handle_fasteoi_irq' handler that only clears the request on the way out. Because MIPS processor interrupt inputs, one of which the I/O ASIC's interrupt controller is cascaded to, are level-triggered it is recommended that error DMA interrupt action handlers are registered with the IRQF_ONESHOT flag set so that they are run with the interrupt line masked. This change removes the export of clear_ioasic_dma_irq that now does not have to be called by device drivers to clear interrupts explicitly anymore. Originally these interrupts were cleared in the .end handler of the `irq_chip' structure, before it was removed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5874/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2013-10-29 21:24:42 +01:00
..
prom	MIPS: Optimize current_cpu_type() for better code.	2013-09-17 18:50:53 +02:00
ecc-berr.c
int-handler.S	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00
ioasic-irq.c	MIPS: DECstation I/O ASIC DMA interrupt classes	2013-10-29 21:24:42 +01:00
kn01-berr.c
kn02-irq.c
kn02xa-berr.c	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00
Makefile	MIPS: DEC: remove unbuildable promcon.c	2013-06-18 00:31:29 +02:00
Platform
reset.c
setup.c	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00
tc.c
time.c	MIPS: DECstation HRT initialization rearrangement	2013-09-13 11:56:13 +02:00
wbflush.c	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00