forked from luck/tmp_suning_uos_patched
8dccafaa28
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
450 lines
11 KiB
Plaintext
450 lines
11 KiB
Plaintext
/*
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* Copyright (C) 2016 NXP Semiconductors.
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* Author: Fabio Estevam <fabio.estevam@nxp.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "imx7s.dtsi"
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/ {
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model = "Warp i.MX7 Board";
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compatible = "warp,imx7s-warp", "fsl,imx7s";
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memory {
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reg = <0x80000000 0x20000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&pinctrl_gpio>;
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autorepeat;
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back {
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label = "Back";
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gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_BACK>;
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wakeup-source;
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};
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};
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reg_brcm: regulator-brcm {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_brcm_reg>;
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regulator-name = "brcm_reg";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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startup-delay-us = <200000>;
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};
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reg_bt: regulator-bt {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_bt_reg>;
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enable-active-high;
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gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
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regulator-name = "bt_reg";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx7-sgtl5000";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,cpu {
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sound-dai = <&sai1>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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};
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};
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};
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&clks {
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assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <884736000>;
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};
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&cpu0 {
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arm-supply = <&sw1a_reg>;
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze3000@8 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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codec: sgtl5000@a {
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#sound-dai-cells = <0>;
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reg = <0x0a>;
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compatible = "fsl,sgtl5000";
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1_mclk>;
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VDDA-supply = <&vgen4_reg>;
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VDDIO-supply = <&vgen4_reg>;
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VDDD-supply = <&vgen2_reg>;
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};
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mpl3115@60 {
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compatible = "fsl,mpl3115";
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reg = <0x60>;
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};
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
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<&clks IMX7D_SAI1_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <0>, <36864000>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <4>;
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keep-power-in-suspend;
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no-1-8-v;
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non-removable;
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vmmc-supply = <®_brcm>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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bus-width = <8>;
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no-1-8-v;
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fsl,tuning-step = <2>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_brcm_reg: brcmreggrp {
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fsl,pins = <
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MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
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>;
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};
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pinctrl_bt_reg: btreggrp {
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fsl,pins = <
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MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
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>;
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};
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pinctrl_gpio: gpiogrp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
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MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
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MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
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MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
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MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
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MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
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MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
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>;
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};
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pinctrl_sai1_mclk: sai1mclkgrp {
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fsl,pins = <
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MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
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MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
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MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
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MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x59
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MX7D_PAD_SD1_CLK__SD1_CLK 0x19
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
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MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x59
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MX7D_PAD_SD3_CLK__SD3_CLK 0x19
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
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MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
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MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
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MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
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MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
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MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
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>;
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};
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};
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&iomuxc_lpsr {
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
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>;
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};
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};
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