forked from luck/tmp_suning_uos_patched
abe45fd9f1
This patch adds the Andestech Internal Vector Interrupt Controller driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual. http://www.andestech.com/product.php?cls=9 Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <nds32_intrinsic.h>
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static void ativic32_ack_irq(struct irq_data *data)
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{
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__nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
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}
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static void ativic32_mask_irq(struct irq_data *data)
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{
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unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
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__nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2);
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}
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static void ativic32_unmask_irq(struct irq_data *data)
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{
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unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
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__nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
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}
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static struct irq_chip ativic32_chip = {
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.name = "ativic32",
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.irq_ack = ativic32_ack_irq,
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.irq_mask = ativic32_mask_irq,
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.irq_unmask = ativic32_unmask_irq,
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};
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static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
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static struct irq_domain *root_domain;
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static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
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irq_hw_number_t hw)
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{
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unsigned long int_trigger_type;
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u32 type;
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struct irq_data *irq_data;
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int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
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irq_data = irq_get_irq_data(virq);
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if (!irq_data)
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return -EINVAL;
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if (int_trigger_type & (BIT(hw))) {
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irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
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type = IRQ_TYPE_EDGE_RISING;
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} else {
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irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);
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type = IRQ_TYPE_LEVEL_HIGH;
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}
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irqd_set_trigger_type(irq_data, type);
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return 0;
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}
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static struct irq_domain_ops ativic32_ops = {
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.map = ativic32_irq_domain_map,
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.xlate = irq_domain_xlate_onecell
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};
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static irq_hw_number_t get_intr_src(void)
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{
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return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> ITYPE_offVECTOR)
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- NDS32_VECTOR_offINTERRUPT;
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}
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asmlinkage void asm_do_IRQ(struct pt_regs *regs)
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{
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irq_hw_number_t hwirq = get_intr_src();
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handle_domain_irq(root_domain, hwirq, regs);
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}
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int __init ativic32_init_irq(struct device_node *node, struct device_node *parent)
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{
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unsigned long int_vec_base, nivic, nr_ints;
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if (WARN(parent, "non-root ativic32 are not supported"))
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return -EINVAL;
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int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
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if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
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panic("Unable to use atcivic32 for this cpu.\n");
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nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
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if (nivic >= ARRAY_SIZE(nivic_map))
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panic("The number of input for ativic32 is not supported.\n");
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nr_ints = nivic_map[nivic];
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root_domain = irq_domain_add_linear(node, nr_ints,
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&ativic32_ops, NULL);
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if (!root_domain)
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panic("%s: unable to create IRQ domain\n", node->full_name);
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return 0;
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}
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IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);
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